derek.holloway
7502bf64a4
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34 lines
1.7 KiB
LLVM
34 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s
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; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar,
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; COM: since, on GPUs, each i1 takes up at least one register and so they should
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; COM: be treated separately.
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define void @scalarize_v2i32(<2 x ptr> %p, <2 x i1> %mask, <2 x i32> %value) {
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; CHECK-LABEL: define void @scalarize_v2i32(
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; CHECK-SAME: <2 x ptr> [[P:%.*]], <2 x i1> [[MASK:%.*]], <2 x i32> [[VALUE:%.*]]) {
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; CHECK-NEXT: [[MASK0:%.*]] = extractelement <2 x i1> [[MASK]], i64 0
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; CHECK-NEXT: br i1 [[MASK0]], label %[[COND_STORE:.*]], label %[[ELSE:.*]]
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; CHECK: [[COND_STORE]]:
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; CHECK-NEXT: [[ELT0:%.*]] = extractelement <2 x i32> [[VALUE]], i64 0
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; CHECK-NEXT: [[PTR0:%.*]] = extractelement <2 x ptr> [[P]], i64 0
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; CHECK-NEXT: store i32 [[ELT0]], ptr [[PTR0]], align 8
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; CHECK-NEXT: br label %[[ELSE]]
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; CHECK: [[ELSE]]:
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; CHECK-NEXT: [[MASK1:%.*]] = extractelement <2 x i1> [[MASK]], i64 1
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; CHECK-NEXT: br i1 [[MASK1]], label %[[COND_STORE1:.*]], label %[[ELSE2:.*]]
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; CHECK: [[COND_STORE1]]:
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; CHECK-NEXT: [[ELT1:%.*]] = extractelement <2 x i32> [[VALUE]], i64 1
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; CHECK-NEXT: [[PTR1:%.*]] = extractelement <2 x ptr> [[P]], i64 1
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; CHECK-NEXT: store i32 [[ELT1]], ptr [[PTR1]], align 8
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; CHECK-NEXT: br label %[[ELSE2]]
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; CHECK: [[ELSE2]]:
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; CHECK-NEXT: ret void
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;
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call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> %value, <2 x ptr> %p, i32 8, <2 x i1> %mask)
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ret void
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}
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declare void @llvm.masked.scatter.v2i32.v2p0(<2 x i32>, <2 x ptr>, i32, <2 x i1>)
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