derek.holloway
7502bf64a4
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98 lines
4.0 KiB
LLVM
98 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S --passes='simplifycfg<hoist-common-insts>' -simplifycfg-hoist-common-skip-limit=0 %s | FileCheck %s --check-prefix=LIMIT0
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; RUN: opt -S --passes='simplifycfg<hoist-common-insts>' -simplifycfg-hoist-common-skip-limit=1 %s | FileCheck %s --check-prefix=LIMIT1
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; RUN: opt -S --passes='simplifycfg<hoist-common-insts>' -simplifycfg-hoist-common-skip-limit=2 %s | FileCheck %s --check-prefix=LIMIT2
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define void @f(i1 %c, ptr nocapture noundef %d, ptr nocapture noundef readonly %m, ptr nocapture noundef readonly %b) {
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; LIMIT0-LABEL: @f(
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; LIMIT0-NEXT: entry:
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; LIMIT0-NEXT: [[TMP0:%.*]] = load i16, ptr [[B:%.*]], align 2
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; LIMIT0-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
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; LIMIT0: if.then:
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; LIMIT0-NEXT: call void @no_side_effects0()
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; LIMIT0-NEXT: [[ADD:%.*]] = add nsw i16 [[TMP0]], 1
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; LIMIT0-NEXT: [[TMP1:%.*]] = load i16, ptr [[M:%.*]], align 2
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; LIMIT0-NEXT: [[U:%.*]] = add i16 [[ADD]], [[TMP1]]
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; LIMIT0-NEXT: br label [[IF_END:%.*]]
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; LIMIT0: if.else:
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; LIMIT0-NEXT: call void @no_side_effects1()
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; LIMIT0-NEXT: [[SUB:%.*]] = sub nsw i16 [[TMP0]], 1
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; LIMIT0-NEXT: [[TMP2:%.*]] = load i16, ptr [[M]], align 2
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; LIMIT0-NEXT: [[V:%.*]] = add i16 [[SUB]], [[TMP2]]
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; LIMIT0-NEXT: br label [[IF_END]]
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; LIMIT0: if.end:
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; LIMIT0-NEXT: [[UV:%.*]] = phi i16 [ [[V]], [[IF_ELSE]] ], [ [[U]], [[IF_THEN]] ]
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; LIMIT0-NEXT: store i16 [[UV]], ptr [[D:%.*]], align 2
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; LIMIT0-NEXT: ret void
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;
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; LIMIT1-LABEL: @f(
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; LIMIT1-NEXT: entry:
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; LIMIT1-NEXT: [[TMP0:%.*]] = load i16, ptr [[B:%.*]], align 2
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; LIMIT1-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
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; LIMIT1: if.then:
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; LIMIT1-NEXT: call void @no_side_effects0()
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; LIMIT1-NEXT: [[ADD:%.*]] = add nsw i16 [[TMP0]], 1
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; LIMIT1-NEXT: [[TMP1:%.*]] = load i16, ptr [[M:%.*]], align 2
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; LIMIT1-NEXT: [[U:%.*]] = add i16 [[ADD]], [[TMP1]]
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; LIMIT1-NEXT: br label [[IF_END:%.*]]
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; LIMIT1: if.else:
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; LIMIT1-NEXT: call void @no_side_effects1()
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; LIMIT1-NEXT: [[SUB:%.*]] = sub nsw i16 [[TMP0]], 1
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; LIMIT1-NEXT: [[TMP2:%.*]] = load i16, ptr [[M]], align 2
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; LIMIT1-NEXT: [[V:%.*]] = add i16 [[SUB]], [[TMP2]]
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; LIMIT1-NEXT: br label [[IF_END]]
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; LIMIT1: if.end:
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; LIMIT1-NEXT: [[UV:%.*]] = phi i16 [ [[V]], [[IF_ELSE]] ], [ [[U]], [[IF_THEN]] ]
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; LIMIT1-NEXT: store i16 [[UV]], ptr [[D:%.*]], align 2
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; LIMIT1-NEXT: ret void
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;
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; LIMIT2-LABEL: @f(
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; LIMIT2-NEXT: entry:
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; LIMIT2-NEXT: [[TMP0:%.*]] = load i16, ptr [[B:%.*]], align 2
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; LIMIT2-NEXT: [[TMP1:%.*]] = load i16, ptr [[M:%.*]], align 2
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; LIMIT2-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
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; LIMIT2: if.then:
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; LIMIT2-NEXT: call void @no_side_effects0()
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; LIMIT2-NEXT: [[ADD:%.*]] = add nsw i16 [[TMP0]], 1
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; LIMIT2-NEXT: [[U:%.*]] = add i16 [[ADD]], [[TMP1]]
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; LIMIT2-NEXT: br label [[IF_END:%.*]]
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; LIMIT2: if.else:
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; LIMIT2-NEXT: call void @no_side_effects1()
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; LIMIT2-NEXT: [[SUB:%.*]] = sub nsw i16 [[TMP0]], 1
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; LIMIT2-NEXT: [[V:%.*]] = add i16 [[SUB]], [[TMP1]]
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; LIMIT2-NEXT: br label [[IF_END]]
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; LIMIT2: if.end:
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; LIMIT2-NEXT: [[UV:%.*]] = phi i16 [ [[V]], [[IF_ELSE]] ], [ [[U]], [[IF_THEN]] ]
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; LIMIT2-NEXT: store i16 [[UV]], ptr [[D:%.*]], align 2
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; LIMIT2-NEXT: ret void
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;
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entry:
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br i1 %c, label %if.then, label %if.else
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if.then:
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%0 = load i16, ptr %b, align 2
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call void @no_side_effects0()
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%add = add nsw i16 %0, 1
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%1 = load i16, ptr %m, align 2
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%u = add i16 %add, %1
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br label %if.end
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if.else:
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%2 = load i16, ptr %b, align 2
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call void @no_side_effects1()
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%sub = sub nsw i16 %2, 1
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%3 = load i16, ptr %m, align 2
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%v = add i16 %sub, %3
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br label %if.end
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if.end:
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%uv = phi i16 [ %v, %if.else ], [ %u, %if.then ]
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store i16 %uv, ptr %d, align 2
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ret void
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}
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declare void @side_effects0()
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declare void @side_effects1()
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declare void @no_side_effects0() readonly nounwind willreturn
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declare void @no_side_effects1() readonly nounwind willreturn
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