derek.holloway
7502bf64a4
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126 lines
6.5 KiB
LLVM
126 lines
6.5 KiB
LLVM
; RUN: not llvm-as %s -disable-output 2>&1 | FileCheck %s
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declare void @llvm.amdgcn.cs.chain(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) noreturn
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declare i32 @llvm.amdgcn.set.inactive.chain.arg(i32, i32) convergent willreturn nofree nocallback readnone
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define amdgpu_cs_chain void @bad_flags(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 %flags) {
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %flags
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; CHECK-NEXT: @llvm.amdgcn.cs.chain
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call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 %flags)
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unreachable
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}
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define amdgpu_cs_chain void @bad_vgpr_args(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } inreg %vgpr) {
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; CHECK: VGPR arguments must not have the `inreg` attribute
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; CHECK-NEXT: @llvm.amdgcn.cs.chain
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call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } inreg %vgpr, i32 0)
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unreachable
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}
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define amdgpu_cs_chain void @bad_sgpr_args(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr) {
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; CHECK: SGPR arguments must have the `inreg` attribute
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; CHECK-NEXT: @llvm.amdgcn.cs.chain
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call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)
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unreachable
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}
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define amdgpu_cs_chain void @bad_exec(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 %flags) {
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; CHECK: Intrinsic called with incompatible signature
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; CHECK-NEXT: @llvm.amdgcn.cs.chain
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call void(ptr, <4 x i32>, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, <4 x i32> %sgpr, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 %flags)
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unreachable
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}
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define amdgpu_cs_chain void @not_unreachable(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
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; CHECK: llvm.amdgcn.cs.chain must be followed by unreachable
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; CHECK-NEXT: @llvm.amdgcn.cs.chain
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call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)
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ret void
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}
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define void @bad_caller_default_cc(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
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; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions
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; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
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%unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)
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; CHECK: Intrinsic cannot be called from functions with this calling convention
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; CHECK-NEXT: @llvm.amdgcn.cs.chain
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call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)
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unreachable
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}
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define amdgpu_kernel void @bad_caller_amdgpu_kernel(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
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; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions
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; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
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%unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)
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; CHECK: Intrinsic cannot be called from functions with this calling convention
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; CHECK-NEXT: @llvm.amdgcn.cs.chain
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call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)
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unreachable
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}
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define amdgpu_gfx void @bad_caller_amdgpu_gfx(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
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; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions
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; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
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%unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)
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; CHECK: Intrinsic cannot be called from functions with this calling convention
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; CHECK-NEXT: @llvm.amdgcn.cs.chain
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call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)
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unreachable
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}
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define amdgpu_vs void @bad_caller_amdgpu_vs(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
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; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions
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; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
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%unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)
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; Unlike llvm.amdgcn.set.inactive.chain.arg, llvm.amdgcn.cs.chain may be called from amdgpu_vs functions.
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ret void
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}
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define amdgpu_cs void @bad_caller_amdgpu_cs(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
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; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions
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; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
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%unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)
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; Unlike llvm.amdgcn.set.inactive.chain.arg, llvm.amdgcn.cs.chain may be called from amdgpu_cs functions.
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ret void
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}
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define amdgpu_cs_chain void @set_inactive_chain_arg_sgpr(ptr addrspace(1) %out, i32 %active, i32 inreg %inactive) {
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; CHECK: Value for inactive lanes must be a VGPR function argument
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; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
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%tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 %inactive) #0
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store i32 %tmp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_cs_chain void @set_inactive_chain_arg_const(ptr addrspace(1) %out, i32 %active) {
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; CHECK: Value for inactive lanes must be a function argument
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; CHECK-NEXT: llvm.amdgcn.set.inactive.chain.arg
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%tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 29) #0
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store i32 %tmp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_cs_chain void @set_inactive_chain_arg_computed(ptr addrspace(1) %out, i32 %active) {
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; CHECK: Value for inactive lanes must be a function argument
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; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
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%inactive = add i32 %active, 127
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%tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 %inactive) #0
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store i32 %tmp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_cs_chain void @set_inactive_chain_arg_inreg(ptr addrspace(1) %out, i32 %active, i32 %inactive) {
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; CHECK: Value for inactive lanes must not have the `inreg` attribute
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; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
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%tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 inreg %inactive) #0
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store i32 %tmp, ptr addrspace(1) %out
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ret void
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}
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