derek.holloway
7502bf64a4
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68 lines
3.1 KiB
LLVM
68 lines
3.1 KiB
LLVM
; REQUIRES: aarch64-registered-target
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;; There shouldn't be a default -mtune.
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOTUNE
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; RUN: llc < %s -mtriple=aarch64 -mtune=generic | FileCheck %s --check-prefixes=CHECK-TUNE-GENERIC
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; RUN: llc < %s -mtriple=aarch64 -mtune=apple-m5 | FileCheck %s --check-prefixes=CHECK-TUNE-APPLE-M5
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;; Check interaction between mcpu and mtune.
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; RUN: llc < %s -mtriple=aarch64 -mcpu=apple-m5 | FileCheck %s --check-prefixes=CHECK-TUNE-APPLE-M5
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; RUN: llc < %s -mtriple=aarch64 -mcpu=apple-m5 -mtune=generic | FileCheck %s --check-prefixes=CHECK-TUNE-GENERIC
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;; Test -mtune=help
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; RUN: llc -mtriple=aarch64 -mtune=help 2>&1 | FileCheck %s --check-prefixes=CHECK-TUNE-HELP,CHECK-TUNE-HELP-NO-COMPILE
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; RUN: llc -mtriple=aarch64 -mtune=help -o %t.s 2>&1 | FileCheck %s --check-prefixes=CHECK-TUNE-HELP,CHECK-TUNE-HELP-NO-COMPILE
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; RUN: llc < %s -mtriple=aarch64 -mtune=help 2>&1 | FileCheck %s --check-prefixes=CHECK-TUNE-HELP,CHECK-TUNE-HELP-NO-COMPILE
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; RUN: llc < %s -mtriple=aarch64 -mtune=help -o %t.s 2>&1 | FileCheck %s --check-prefixes=CHECK-TUNE-HELP,CHECK-TUNE-HELP-NO-COMPILE
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;; Using default target triple for -mtune=help
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; RUN: llc -mtune=help 2>&1 | FileCheck %s --check-prefixes=CHECK-TUNE-HELP,CHECK-TUNE-HELP-NO-COMPILE
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; RUN: llc < %s -mtune=help 2>&1 | FileCheck %s --check-prefixes=CHECK-TUNE-HELP,CHECK-TUNE-HELP-NO-COMPILE
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; CHECK-TUNE-HELP: Available CPUs for this target:
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; CHECK-TUNE-HELP: Available features for this target:
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;; To check we dont compile the file
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; CHECK-TUNE-HELP-NO-COMPILE-NOT: zero_cycle_regmove_FPR32:
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;; A test case that depends on `FeatureZCRegMoveFPR128` tuning feature, to enable -mtune verification
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;; through codegen effects. Taken from: llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
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define void @zero_cycle_regmove_FPR32(float %a, float %b, float %c, float %d) {
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; CHECK-NOTUNE-LABEL: zero_cycle_regmove_FPR32:
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; CHECK-NOTUNE: fmov s0, s2
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; CHECK-NOTUNE-NEXT: fmov s1, s3
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; CHECK-NOTUNE-NEXT: fmov s8, s3
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; CHECK-NOTUNE-NEXT: fmov s9, s2
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; CHECK-NOTUNE-NEXT: bl foo_float
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; CHECK-NOTUNE-NEXT: fmov s0, s9
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; CHECK-NOTUNE-NEXT: fmov s1, s8
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; CHECK-NOTUNE-NEXT: bl foo_float
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;
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; CHECK-TUNE-GENERIC-LABEL: zero_cycle_regmove_FPR32:
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; CHECK-TUNE-GENERIC: fmov s0, s2
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; CHECK-TUNE-GENERIC-NEXT: fmov s1, s3
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; CHECK-TUNE-GENERIC-NEXT: fmov s8, s3
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; CHECK-TUNE-GENERIC-NEXT: fmov s9, s2
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; CHECK-TUNE-GENERIC-NEXT: bl foo_float
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; CHECK-TUNE-GENERIC-NEXT: fmov s0, s9
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; CHECK-TUNE-GENERIC-NEXT: fmov s1, s8
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; CHECK-TUNE-GENERIC-NEXT: bl foo_float
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;
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; CHECK-TUNE-APPLE-M5-LABEL: zero_cycle_regmove_FPR32:
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; CHECK-TUNE-APPLE-M5: mov v8.16b, v3.16b
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; CHECK-TUNE-APPLE-M5-NEXT: mov v9.16b, v2.16b
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; CHECK-TUNE-APPLE-M5-NEXT: mov v0.16b, v2.16b
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; CHECK-TUNE-APPLE-M5-NEXT: mov v1.16b, v3.16b
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; CHECK-TUNE-APPLE-M5-NEXT: bl foo_float
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; CHECK-TUNE-APPLE-M5-NEXT: mov v0.16b, v9.16b
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; CHECK-TUNE-APPLE-M5-NEXT: mov v1.16b, v8.16b
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; CHECK-TUNE-APPLE-M5-NEXT: bl foo_float
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entry:
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%call = call float @foo_float(float %c, float %d)
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%call1 = call float @foo_float(float %c, float %d)
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unreachable
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}
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declare float @foo_float(float, float)
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