derek.holloway
7502bf64a4
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73 lines
4.2 KiB
ArmAsm
73 lines
4.2 KiB
ArmAsm
# REQUIRES: aarch64-registered-target
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// Test for omitting OperandType::OPERAND_SHIFT_MSL
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// MOVIv2s_msl: MOVI vd, #imm{, shift}
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# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv4s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv4s_msl_latency
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# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv4s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv4s_msl_throughput
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# MOVIv4s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv4s_msl opcode
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// TODO: Add test to check if the immediate value is correct when serial execution strategy is added for MOVIv4s_msl
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# MOVIv4s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv4s_msl opcode
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# MOVIv4s_msl_throughput: ---
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# MOVIv4s_msl_throughput-NEXT: mode: inverse_throughput
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# MOVIv4s_msl_throughput-NEXT: key:
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# MOVIv4s_msl_throughput-NEXT: instructions:
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# MOVIv4s_msl_throughput-NEXT: MOVIv4s_msl [[REG1:Q[0-9]+|LR]] i_0x1 i_0x108
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# MOVIv4s_msl_throughput: ...
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// MOVIv2s_msl: MOVI vd, #imm{, shift}
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# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_latency
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# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput
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# MOVIv2s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode
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// TODO: Add test to check if the immediate value is correct when serial execution strategy is added for MOVIv2s_msl
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# MOVIv2s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode
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# MOVIv2s_msl_throughput: ---
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# MOVIv2s_msl_throughput-NEXT: mode: inverse_throughput
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# MOVIv2s_msl_throughput-NEXT: key:
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# MOVIv2s_msl_throughput-NEXT: instructions:
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# MOVIv2s_msl_throughput-NEXT: MOVIv2s_msl [[REG1:D[0-9]+|LR]] i_0x1 i_0x108
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# MOVIv2s_msl_throughput: ...
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// Test for omitting OperandType::OPERAND_PCREL
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// LDRDl: LDRD ldr1, ldr2, [pc, #imm]
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# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=LDRDl 2>&1 | FileCheck %s --check-prefix=LDRDl_latency
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# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=LDRDl 2>&1 | FileCheck %s --check-prefix=LDRDl_throughput
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# LDRDl_latency-NOT: Not all operands were initialized by the snippet generator for LDRDl opcodes
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# LDRDl_throughput-NOT: Not all operands were initialized by the snippet generator for LDRDl opcodes
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# LDRDl_throughput: ---
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# LDRDl_throughput-NEXT: mode: inverse_throughput
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# LDRDl_throughput-NEXT: key:
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# LDRDl_throughput-NEXT: instructions:
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# LDRDl_throughput-NEXT: LDRDl [[REG1:D[0-9]+|LR]] i_0x8
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# LDRDl_throughput: ...
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// Test for omitting OperandType::OPERAND_IMPLICIT_IMM_0
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// UMOVvi16_idx0: UMOV wd, vn.h[index]
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# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_latency
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# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_throughput
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# UMOVvi16_idx0_latency-NOT: UMOVvi16_idx0: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode.
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# UMOVvi16_idx0_throughput-NOT: UMOVvi16_idx0: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode.
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# UMOVvi16_idx0_throughput: ---
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# UMOVvi16_idx0_throughput-NEXT: mode: inverse_throughput
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# UMOVvi16_idx0_throughput-NEXT: key:
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# UMOVvi16_idx0_throughput-NEXT: instructions:
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# UMOVvi16_idx0_throughput-NEXT: UMOVvi16_idx0 [[REG1:W[0-9]+|LR]] [[REG2:Q[0-9]+|LR]] i_0x0
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# UMOVvi16_idx0_throughput: ...
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