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822 lines
34 KiB
ArmAsm
822 lines
34 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 --timeline --timeline-max-iterations=4 < %s | FileCheck %s
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|
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# LLVM-MCA-BEGIN GPR32-bit
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ldr w0, [sp]
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add x0, x0, x0
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# LLVM-MCA-END
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|
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# LLVM-MCA-BEGIN FPR8-bit
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ldr b0, [sp]
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fadd d0, d0, d0
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# LLVM-MCA-END
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|
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# LLVM-MCA-BEGIN FPR16-bit
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ldr h0, [sp]
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fadd d0, d0, d0
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# LLVM-MCA-END
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|
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# LLVM-MCA-BEGIN FPR32-bit
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ldr s0, [sp]
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fadd d0, d0, d0
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# LLVM-MCA-END
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|
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# LLVM-MCA-BEGIN SIMD64-bit-b
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ld1 {v0.8b}, [sp]
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add v0.16b, v0.16b, v0.16b
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# LLVM-MCA-END
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# LLVM-MCA-BEGIN SIMD64-bit-h
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ld1 {v0.4h}, [sp]
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add v0.8h, v0.8h, v0.8h
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# LLVM-MCA-END
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# LLVM-MCA-BEGIN SIMD64-bit-s
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ld1 {v0.2s}, [sp]
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add v0.4s, v0.4s, v0.4s
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# LLVM-MCA-END
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# LLVM-MCA-BEGIN SIMD64-bit-d
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ld1 {v0.1d}, [sp]
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add v0.2d, v0.2d, v0.2d
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# LLVM-MCA-END
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# LLVM-MCA-BEGIN ins
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ins v0.b[0], v1.b[1]
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add v0.16b, v0.16b, v0.16b
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# LLVM-MCA-END
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# LLVM-MCA-BEGIN lanewise-load
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ld1 {v0.b}[0], [sp]
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add v0.16b, v0.16b, v0.16b
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# LLVM-MCA-END
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# CHECK: [0] Code Region - GPR32-bit
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# CHECK: Iterations: 100
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# CHECK-NEXT: Instructions: 200
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# CHECK-NEXT: Total Cycles: 41
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# CHECK-NEXT: Total uOps: 200
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|
|
|
# CHECK: Dispatch Width: 8
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|
# CHECK-NEXT: uOps Per Cycle: 4.88
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|
# CHECK-NEXT: IPC: 4.88
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|
# CHECK-NEXT: Block RThroughput: 0.3
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|
|
|
# CHECK: Instruction Info:
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|
# CHECK-NEXT: [1]: #uOps
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|
# CHECK-NEXT: [2]: Latency
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|
# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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|
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 4 0.33 * ldr w0, [sp]
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# CHECK-NEXT: 1 1 0.25 add x0, x0, x0
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|
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# CHECK: Resources:
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# CHECK-NEXT: [0.0] - V1UnitB
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# CHECK-NEXT: [0.1] - V1UnitB
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# CHECK-NEXT: [1.0] - V1UnitD
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# CHECK-NEXT: [1.1] - V1UnitD
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|
# CHECK-NEXT: [2.0] - V1UnitFlg
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|
# CHECK-NEXT: [2.1] - V1UnitFlg
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|
# CHECK-NEXT: [2.2] - V1UnitFlg
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|
# CHECK-NEXT: [3] - V1UnitL2
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# CHECK-NEXT: [4.0] - V1UnitL01
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# CHECK-NEXT: [4.1] - V1UnitL01
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|
# CHECK-NEXT: [5] - V1UnitM0
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# CHECK-NEXT: [6] - V1UnitM1
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|
# CHECK-NEXT: [7.0] - V1UnitS
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|
# CHECK-NEXT: [7.1] - V1UnitS
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|
# CHECK-NEXT: [8] - V1UnitV0
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|
# CHECK-NEXT: [9] - V1UnitV1
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|
# CHECK-NEXT: [10] - V1UnitV2
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|
# CHECK-NEXT: [11] - V1UnitV3
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|
|
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# CHECK: Resource pressure per iteration:
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|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
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# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 0.22 0.22 0.28 0.28 - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
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# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - - - - - ldr w0, [sp]
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# CHECK-NEXT: - - - - - - - - - - 0.22 0.22 0.28 0.28 - - - - add x0, x0, x0
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|
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# CHECK: Timeline view:
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# CHECK-NEXT: Index 012345678
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# CHECK: [0,0] DeeeeER . ldr w0, [sp]
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# CHECK-NEXT: [0,1] D====eER. add x0, x0, x0
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# CHECK-NEXT: [1,0] DeeeeE-R. ldr w0, [sp]
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# CHECK-NEXT: [1,1] D====eER. add x0, x0, x0
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# CHECK-NEXT: [2,0] DeeeeE-R. ldr w0, [sp]
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# CHECK-NEXT: [2,1] D====eER. add x0, x0, x0
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# CHECK-NEXT: [3,0] D=eeeeER. ldr w0, [sp]
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# CHECK-NEXT: [3,1] D=====eER add x0, x0, x0
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|
|
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# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
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|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 4 1.3 1.3 0.5 ldr w0, [sp]
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# CHECK-NEXT: 1. 4 5.3 0.0 0.0 add x0, x0, x0
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# CHECK-NEXT: 8 3.3 0.6 0.3 <total>
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# CHECK: [1] Code Region - FPR8-bit
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|
|
|
# CHECK: Iterations: 100
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|
# CHECK-NEXT: Instructions: 200
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|
# CHECK-NEXT: Total Cycles: 44
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# CHECK-NEXT: Total uOps: 200
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|
|
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# CHECK: Dispatch Width: 8
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# CHECK-NEXT: uOps Per Cycle: 4.55
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# CHECK-NEXT: IPC: 4.55
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# CHECK-NEXT: Block RThroughput: 0.3
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|
|
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 6 0.33 * ldr b0, [sp]
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# CHECK-NEXT: 1 2 0.25 fadd d0, d0, d0
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# CHECK: Resources:
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# CHECK-NEXT: [0.0] - V1UnitB
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# CHECK-NEXT: [0.1] - V1UnitB
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# CHECK-NEXT: [1.0] - V1UnitD
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# CHECK-NEXT: [1.1] - V1UnitD
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# CHECK-NEXT: [2.0] - V1UnitFlg
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|
# CHECK-NEXT: [2.1] - V1UnitFlg
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|
# CHECK-NEXT: [2.2] - V1UnitFlg
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|
# CHECK-NEXT: [3] - V1UnitL2
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# CHECK-NEXT: [4.0] - V1UnitL01
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# CHECK-NEXT: [4.1] - V1UnitL01
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# CHECK-NEXT: [5] - V1UnitM0
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# CHECK-NEXT: [6] - V1UnitM1
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# CHECK-NEXT: [7.0] - V1UnitS
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# CHECK-NEXT: [7.1] - V1UnitS
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# CHECK-NEXT: [8] - V1UnitV0
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# CHECK-NEXT: [9] - V1UnitV1
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|
# CHECK-NEXT: [10] - V1UnitV2
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# CHECK-NEXT: [11] - V1UnitV3
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|
|
|
# CHECK: Resource pressure per iteration:
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|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
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# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - 0.25 0.25 0.25 0.25
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
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# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - - - - - ldr b0, [sp]
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# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
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|
|
|
# CHECK: Timeline view:
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|
# CHECK-NEXT: 01
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# CHECK-NEXT: Index 0123456789
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|
|
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# CHECK: [0,0] DeeeeeeER .. ldr b0, [sp]
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# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
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# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr b0, [sp]
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# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
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|
# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr b0, [sp]
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# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
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|
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr b0, [sp]
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# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
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|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr b0, [sp]
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|
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
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# CHECK-NEXT: 8 4.3 0.6 0.6 <total>
|
|
|
|
# CHECK: [2] Code Region - FPR16-bit
|
|
|
|
# CHECK: Iterations: 100
|
|
# CHECK-NEXT: Instructions: 200
|
|
# CHECK-NEXT: Total Cycles: 44
|
|
# CHECK-NEXT: Total uOps: 200
|
|
|
|
# CHECK: Dispatch Width: 8
|
|
# CHECK-NEXT: uOps Per Cycle: 4.55
|
|
# CHECK-NEXT: IPC: 4.55
|
|
# CHECK-NEXT: Block RThroughput: 0.3
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
|
# CHECK-NEXT: 1 6 0.33 * ldr h0, [sp]
|
|
# CHECK-NEXT: 1 2 0.25 fadd d0, d0, d0
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - V1UnitB
|
|
# CHECK-NEXT: [0.1] - V1UnitB
|
|
# CHECK-NEXT: [1.0] - V1UnitD
|
|
# CHECK-NEXT: [1.1] - V1UnitD
|
|
# CHECK-NEXT: [2.0] - V1UnitFlg
|
|
# CHECK-NEXT: [2.1] - V1UnitFlg
|
|
# CHECK-NEXT: [2.2] - V1UnitFlg
|
|
# CHECK-NEXT: [3] - V1UnitL2
|
|
# CHECK-NEXT: [4.0] - V1UnitL01
|
|
# CHECK-NEXT: [4.1] - V1UnitL01
|
|
# CHECK-NEXT: [5] - V1UnitM0
|
|
# CHECK-NEXT: [6] - V1UnitM1
|
|
# CHECK-NEXT: [7.0] - V1UnitS
|
|
# CHECK-NEXT: [7.1] - V1UnitS
|
|
# CHECK-NEXT: [8] - V1UnitV0
|
|
# CHECK-NEXT: [9] - V1UnitV1
|
|
# CHECK-NEXT: [10] - V1UnitV2
|
|
# CHECK-NEXT: [11] - V1UnitV3
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - 0.25 0.25 0.25 0.25
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - - - - - ldr h0, [sp]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
|
|
|
|
# CHECK: Timeline view:
|
|
# CHECK-NEXT: 01
|
|
# CHECK-NEXT: Index 0123456789
|
|
|
|
# CHECK: [0,0] DeeeeeeER .. ldr h0, [sp]
|
|
# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
|
|
# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr h0, [sp]
|
|
# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
|
|
# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr h0, [sp]
|
|
# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
|
|
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr h0, [sp]
|
|
# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
|
|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr h0, [sp]
|
|
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
|
|
# CHECK-NEXT: 8 4.3 0.6 0.6 <total>
|
|
|
|
# CHECK: [3] Code Region - FPR32-bit
|
|
|
|
# CHECK: Iterations: 100
|
|
# CHECK-NEXT: Instructions: 200
|
|
# CHECK-NEXT: Total Cycles: 44
|
|
# CHECK-NEXT: Total uOps: 200
|
|
|
|
# CHECK: Dispatch Width: 8
|
|
# CHECK-NEXT: uOps Per Cycle: 4.55
|
|
# CHECK-NEXT: IPC: 4.55
|
|
# CHECK-NEXT: Block RThroughput: 0.3
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
|
# CHECK-NEXT: 1 6 0.33 * ldr s0, [sp]
|
|
# CHECK-NEXT: 1 2 0.25 fadd d0, d0, d0
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - V1UnitB
|
|
# CHECK-NEXT: [0.1] - V1UnitB
|
|
# CHECK-NEXT: [1.0] - V1UnitD
|
|
# CHECK-NEXT: [1.1] - V1UnitD
|
|
# CHECK-NEXT: [2.0] - V1UnitFlg
|
|
# CHECK-NEXT: [2.1] - V1UnitFlg
|
|
# CHECK-NEXT: [2.2] - V1UnitFlg
|
|
# CHECK-NEXT: [3] - V1UnitL2
|
|
# CHECK-NEXT: [4.0] - V1UnitL01
|
|
# CHECK-NEXT: [4.1] - V1UnitL01
|
|
# CHECK-NEXT: [5] - V1UnitM0
|
|
# CHECK-NEXT: [6] - V1UnitM1
|
|
# CHECK-NEXT: [7.0] - V1UnitS
|
|
# CHECK-NEXT: [7.1] - V1UnitS
|
|
# CHECK-NEXT: [8] - V1UnitV0
|
|
# CHECK-NEXT: [9] - V1UnitV1
|
|
# CHECK-NEXT: [10] - V1UnitV2
|
|
# CHECK-NEXT: [11] - V1UnitV3
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - 0.25 0.25 0.25 0.25
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - - - - - ldr s0, [sp]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
|
|
|
|
# CHECK: Timeline view:
|
|
# CHECK-NEXT: 01
|
|
# CHECK-NEXT: Index 0123456789
|
|
|
|
# CHECK: [0,0] DeeeeeeER .. ldr s0, [sp]
|
|
# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
|
|
# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr s0, [sp]
|
|
# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
|
|
# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr s0, [sp]
|
|
# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
|
|
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr s0, [sp]
|
|
# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
|
|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr s0, [sp]
|
|
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
|
|
# CHECK-NEXT: 8 4.3 0.6 0.6 <total>
|
|
|
|
# CHECK: [4] Code Region - SIMD64-bit-b
|
|
|
|
# CHECK: Iterations: 100
|
|
# CHECK-NEXT: Instructions: 200
|
|
# CHECK-NEXT: Total Cycles: 44
|
|
# CHECK-NEXT: Total uOps: 200
|
|
|
|
# CHECK: Dispatch Width: 8
|
|
# CHECK-NEXT: uOps Per Cycle: 4.55
|
|
# CHECK-NEXT: IPC: 4.55
|
|
# CHECK-NEXT: Block RThroughput: 0.3
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
|
# CHECK-NEXT: 1 6 0.33 * ld1 { v0.8b }, [sp]
|
|
# CHECK-NEXT: 1 2 0.25 add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - V1UnitB
|
|
# CHECK-NEXT: [0.1] - V1UnitB
|
|
# CHECK-NEXT: [1.0] - V1UnitD
|
|
# CHECK-NEXT: [1.1] - V1UnitD
|
|
# CHECK-NEXT: [2.0] - V1UnitFlg
|
|
# CHECK-NEXT: [2.1] - V1UnitFlg
|
|
# CHECK-NEXT: [2.2] - V1UnitFlg
|
|
# CHECK-NEXT: [3] - V1UnitL2
|
|
# CHECK-NEXT: [4.0] - V1UnitL01
|
|
# CHECK-NEXT: [4.1] - V1UnitL01
|
|
# CHECK-NEXT: [5] - V1UnitM0
|
|
# CHECK-NEXT: [6] - V1UnitM1
|
|
# CHECK-NEXT: [7.0] - V1UnitS
|
|
# CHECK-NEXT: [7.1] - V1UnitS
|
|
# CHECK-NEXT: [8] - V1UnitV0
|
|
# CHECK-NEXT: [9] - V1UnitV1
|
|
# CHECK-NEXT: [10] - V1UnitV2
|
|
# CHECK-NEXT: [11] - V1UnitV3
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - 0.25 0.25 0.25 0.25
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - - - - - ld1 { v0.8b }, [sp]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Timeline view:
|
|
# CHECK-NEXT: 01
|
|
# CHECK-NEXT: Index 0123456789
|
|
|
|
# CHECK: [0,0] DeeeeeeER .. ld1 { v0.8b }, [sp]
|
|
# CHECK-NEXT: [0,1] D======eeER. add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
|
|
# CHECK-NEXT: [1,1] D======eeER. add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
|
|
# CHECK-NEXT: [2,1] D======eeER. add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.8b }, [sp]
|
|
# CHECK-NEXT: [3,1] D=======eeER add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.8b }, [sp]
|
|
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: 8 4.3 0.6 0.6 <total>
|
|
|
|
# CHECK: [5] Code Region - SIMD64-bit-h
|
|
|
|
# CHECK: Iterations: 100
|
|
# CHECK-NEXT: Instructions: 200
|
|
# CHECK-NEXT: Total Cycles: 44
|
|
# CHECK-NEXT: Total uOps: 200
|
|
|
|
# CHECK: Dispatch Width: 8
|
|
# CHECK-NEXT: uOps Per Cycle: 4.55
|
|
# CHECK-NEXT: IPC: 4.55
|
|
# CHECK-NEXT: Block RThroughput: 0.3
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
|
# CHECK-NEXT: 1 6 0.33 * ld1 { v0.4h }, [sp]
|
|
# CHECK-NEXT: 1 2 0.25 add v0.8h, v0.8h, v0.8h
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - V1UnitB
|
|
# CHECK-NEXT: [0.1] - V1UnitB
|
|
# CHECK-NEXT: [1.0] - V1UnitD
|
|
# CHECK-NEXT: [1.1] - V1UnitD
|
|
# CHECK-NEXT: [2.0] - V1UnitFlg
|
|
# CHECK-NEXT: [2.1] - V1UnitFlg
|
|
# CHECK-NEXT: [2.2] - V1UnitFlg
|
|
# CHECK-NEXT: [3] - V1UnitL2
|
|
# CHECK-NEXT: [4.0] - V1UnitL01
|
|
# CHECK-NEXT: [4.1] - V1UnitL01
|
|
# CHECK-NEXT: [5] - V1UnitM0
|
|
# CHECK-NEXT: [6] - V1UnitM1
|
|
# CHECK-NEXT: [7.0] - V1UnitS
|
|
# CHECK-NEXT: [7.1] - V1UnitS
|
|
# CHECK-NEXT: [8] - V1UnitV0
|
|
# CHECK-NEXT: [9] - V1UnitV1
|
|
# CHECK-NEXT: [10] - V1UnitV2
|
|
# CHECK-NEXT: [11] - V1UnitV3
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - 0.25 0.25 0.25 0.25
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - - - - - ld1 { v0.4h }, [sp]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.8h, v0.8h, v0.8h
|
|
|
|
# CHECK: Timeline view:
|
|
# CHECK-NEXT: 01
|
|
# CHECK-NEXT: Index 0123456789
|
|
|
|
# CHECK: [0,0] DeeeeeeER .. ld1 { v0.4h }, [sp]
|
|
# CHECK-NEXT: [0,1] D======eeER. add v0.8h, v0.8h, v0.8h
|
|
# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
|
|
# CHECK-NEXT: [1,1] D======eeER. add v0.8h, v0.8h, v0.8h
|
|
# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
|
|
# CHECK-NEXT: [2,1] D======eeER. add v0.8h, v0.8h, v0.8h
|
|
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.4h }, [sp]
|
|
# CHECK-NEXT: [3,1] D=======eeER add v0.8h, v0.8h, v0.8h
|
|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.4h }, [sp]
|
|
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.8h, v0.8h, v0.8h
|
|
# CHECK-NEXT: 8 4.3 0.6 0.6 <total>
|
|
|
|
# CHECK: [6] Code Region - SIMD64-bit-s
|
|
|
|
# CHECK: Iterations: 100
|
|
# CHECK-NEXT: Instructions: 200
|
|
# CHECK-NEXT: Total Cycles: 44
|
|
# CHECK-NEXT: Total uOps: 200
|
|
|
|
# CHECK: Dispatch Width: 8
|
|
# CHECK-NEXT: uOps Per Cycle: 4.55
|
|
# CHECK-NEXT: IPC: 4.55
|
|
# CHECK-NEXT: Block RThroughput: 0.3
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
|
# CHECK-NEXT: 1 6 0.33 * ld1 { v0.2s }, [sp]
|
|
# CHECK-NEXT: 1 2 0.25 add v0.4s, v0.4s, v0.4s
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - V1UnitB
|
|
# CHECK-NEXT: [0.1] - V1UnitB
|
|
# CHECK-NEXT: [1.0] - V1UnitD
|
|
# CHECK-NEXT: [1.1] - V1UnitD
|
|
# CHECK-NEXT: [2.0] - V1UnitFlg
|
|
# CHECK-NEXT: [2.1] - V1UnitFlg
|
|
# CHECK-NEXT: [2.2] - V1UnitFlg
|
|
# CHECK-NEXT: [3] - V1UnitL2
|
|
# CHECK-NEXT: [4.0] - V1UnitL01
|
|
# CHECK-NEXT: [4.1] - V1UnitL01
|
|
# CHECK-NEXT: [5] - V1UnitM0
|
|
# CHECK-NEXT: [6] - V1UnitM1
|
|
# CHECK-NEXT: [7.0] - V1UnitS
|
|
# CHECK-NEXT: [7.1] - V1UnitS
|
|
# CHECK-NEXT: [8] - V1UnitV0
|
|
# CHECK-NEXT: [9] - V1UnitV1
|
|
# CHECK-NEXT: [10] - V1UnitV2
|
|
# CHECK-NEXT: [11] - V1UnitV3
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - 0.25 0.25 0.25 0.25
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - - - - - ld1 { v0.2s }, [sp]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.4s, v0.4s, v0.4s
|
|
|
|
# CHECK: Timeline view:
|
|
# CHECK-NEXT: 01
|
|
# CHECK-NEXT: Index 0123456789
|
|
|
|
# CHECK: [0,0] DeeeeeeER .. ld1 { v0.2s }, [sp]
|
|
# CHECK-NEXT: [0,1] D======eeER. add v0.4s, v0.4s, v0.4s
|
|
# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
|
|
# CHECK-NEXT: [1,1] D======eeER. add v0.4s, v0.4s, v0.4s
|
|
# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
|
|
# CHECK-NEXT: [2,1] D======eeER. add v0.4s, v0.4s, v0.4s
|
|
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.2s }, [sp]
|
|
# CHECK-NEXT: [3,1] D=======eeER add v0.4s, v0.4s, v0.4s
|
|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.2s }, [sp]
|
|
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.4s, v0.4s, v0.4s
|
|
# CHECK-NEXT: 8 4.3 0.6 0.6 <total>
|
|
|
|
# CHECK: [7] Code Region - SIMD64-bit-d
|
|
|
|
# CHECK: Iterations: 100
|
|
# CHECK-NEXT: Instructions: 200
|
|
# CHECK-NEXT: Total Cycles: 44
|
|
# CHECK-NEXT: Total uOps: 200
|
|
|
|
# CHECK: Dispatch Width: 8
|
|
# CHECK-NEXT: uOps Per Cycle: 4.55
|
|
# CHECK-NEXT: IPC: 4.55
|
|
# CHECK-NEXT: Block RThroughput: 0.3
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
|
# CHECK-NEXT: 1 6 0.33 * ld1 { v0.1d }, [sp]
|
|
# CHECK-NEXT: 1 2 0.25 add v0.2d, v0.2d, v0.2d
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - V1UnitB
|
|
# CHECK-NEXT: [0.1] - V1UnitB
|
|
# CHECK-NEXT: [1.0] - V1UnitD
|
|
# CHECK-NEXT: [1.1] - V1UnitD
|
|
# CHECK-NEXT: [2.0] - V1UnitFlg
|
|
# CHECK-NEXT: [2.1] - V1UnitFlg
|
|
# CHECK-NEXT: [2.2] - V1UnitFlg
|
|
# CHECK-NEXT: [3] - V1UnitL2
|
|
# CHECK-NEXT: [4.0] - V1UnitL01
|
|
# CHECK-NEXT: [4.1] - V1UnitL01
|
|
# CHECK-NEXT: [5] - V1UnitM0
|
|
# CHECK-NEXT: [6] - V1UnitM1
|
|
# CHECK-NEXT: [7.0] - V1UnitS
|
|
# CHECK-NEXT: [7.1] - V1UnitS
|
|
# CHECK-NEXT: [8] - V1UnitV0
|
|
# CHECK-NEXT: [9] - V1UnitV1
|
|
# CHECK-NEXT: [10] - V1UnitV2
|
|
# CHECK-NEXT: [11] - V1UnitV3
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - 0.25 0.25 0.25 0.25
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
|
|
# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 - - - - - - - - ld1 { v0.1d }, [sp]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.2d, v0.2d, v0.2d
|
|
|
|
# CHECK: Timeline view:
|
|
# CHECK-NEXT: 01
|
|
# CHECK-NEXT: Index 0123456789
|
|
|
|
# CHECK: [0,0] DeeeeeeER .. ld1 { v0.1d }, [sp]
|
|
# CHECK-NEXT: [0,1] D======eeER. add v0.2d, v0.2d, v0.2d
|
|
# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
|
|
# CHECK-NEXT: [1,1] D======eeER. add v0.2d, v0.2d, v0.2d
|
|
# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
|
|
# CHECK-NEXT: [2,1] D======eeER. add v0.2d, v0.2d, v0.2d
|
|
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.1d }, [sp]
|
|
# CHECK-NEXT: [3,1] D=======eeER add v0.2d, v0.2d, v0.2d
|
|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.1d }, [sp]
|
|
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.2d, v0.2d, v0.2d
|
|
# CHECK-NEXT: 8 4.3 0.6 0.6 <total>
|
|
|
|
# CHECK: [8] Code Region - ins
|
|
|
|
# CHECK: Iterations: 100
|
|
# CHECK-NEXT: Instructions: 200
|
|
# CHECK-NEXT: Total Cycles: 403
|
|
# CHECK-NEXT: Total uOps: 200
|
|
|
|
# CHECK: Dispatch Width: 8
|
|
# CHECK-NEXT: uOps Per Cycle: 0.50
|
|
# CHECK-NEXT: IPC: 0.50
|
|
# CHECK-NEXT: Block RThroughput: 0.5
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
|
# CHECK-NEXT: 1 2 0.25 mov v0.b[0], v1.b[1]
|
|
# CHECK-NEXT: 1 2 0.25 add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - V1UnitB
|
|
# CHECK-NEXT: [0.1] - V1UnitB
|
|
# CHECK-NEXT: [1.0] - V1UnitD
|
|
# CHECK-NEXT: [1.1] - V1UnitD
|
|
# CHECK-NEXT: [2.0] - V1UnitFlg
|
|
# CHECK-NEXT: [2.1] - V1UnitFlg
|
|
# CHECK-NEXT: [2.2] - V1UnitFlg
|
|
# CHECK-NEXT: [3] - V1UnitL2
|
|
# CHECK-NEXT: [4.0] - V1UnitL01
|
|
# CHECK-NEXT: [4.1] - V1UnitL01
|
|
# CHECK-NEXT: [5] - V1UnitM0
|
|
# CHECK-NEXT: [6] - V1UnitM1
|
|
# CHECK-NEXT: [7.0] - V1UnitS
|
|
# CHECK-NEXT: [7.1] - V1UnitS
|
|
# CHECK-NEXT: [8] - V1UnitV0
|
|
# CHECK-NEXT: [9] - V1UnitV1
|
|
# CHECK-NEXT: [10] - V1UnitV2
|
|
# CHECK-NEXT: [11] - V1UnitV3
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - - 0.50 - 0.50 mov v0.b[0], v1.b[1]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 - add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Timeline view:
|
|
# CHECK-NEXT: 012345678
|
|
# CHECK-NEXT: Index 0123456789
|
|
|
|
# CHECK: [0,0] DeeER. . . . mov v0.b[0], v1.b[1]
|
|
# CHECK-NEXT: [0,1] D==eeER . . . add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [1,0] D====eeER . . . mov v0.b[0], v1.b[1]
|
|
# CHECK-NEXT: [1,1] D======eeER . . add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [2,0] D========eeER . . mov v0.b[0], v1.b[1]
|
|
# CHECK-NEXT: [2,1] D==========eeER. . add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [3,0] D============eeER . mov v0.b[0], v1.b[1]
|
|
# CHECK-NEXT: [3,1] D==============eeER add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 7.0 0.3 0.0 mov v0.b[0], v1.b[1]
|
|
# CHECK-NEXT: 1. 4 9.0 0.0 0.0 add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: 8 8.0 0.1 0.0 <total>
|
|
|
|
# CHECK: [9] Code Region - lanewise-load
|
|
|
|
# CHECK: Iterations: 100
|
|
# CHECK-NEXT: Instructions: 200
|
|
# CHECK-NEXT: Total Cycles: 1003
|
|
# CHECK-NEXT: Total uOps: 300
|
|
|
|
# CHECK: Dispatch Width: 8
|
|
# CHECK-NEXT: uOps Per Cycle: 0.30
|
|
# CHECK-NEXT: IPC: 0.20
|
|
# CHECK-NEXT: Block RThroughput: 0.5
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
|
# CHECK-NEXT: 2 8 0.33 * ld1 { v0.b }[0], [sp]
|
|
# CHECK-NEXT: 1 2 0.25 add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - V1UnitB
|
|
# CHECK-NEXT: [0.1] - V1UnitB
|
|
# CHECK-NEXT: [1.0] - V1UnitD
|
|
# CHECK-NEXT: [1.1] - V1UnitD
|
|
# CHECK-NEXT: [2.0] - V1UnitFlg
|
|
# CHECK-NEXT: [2.1] - V1UnitFlg
|
|
# CHECK-NEXT: [2.2] - V1UnitFlg
|
|
# CHECK-NEXT: [3] - V1UnitL2
|
|
# CHECK-NEXT: [4.0] - V1UnitL01
|
|
# CHECK-NEXT: [4.1] - V1UnitL01
|
|
# CHECK-NEXT: [5] - V1UnitM0
|
|
# CHECK-NEXT: [6] - V1UnitM1
|
|
# CHECK-NEXT: [7.0] - V1UnitS
|
|
# CHECK-NEXT: [7.1] - V1UnitS
|
|
# CHECK-NEXT: [8] - V1UnitV0
|
|
# CHECK-NEXT: [9] - V1UnitV1
|
|
# CHECK-NEXT: [10] - V1UnitV2
|
|
# CHECK-NEXT: [11] - V1UnitV3
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
|
|
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - 0.50 0.50 0.50 0.50
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
|
|
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - 0.50 - 0.50 ld1 { v0.b }[0], [sp]
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 - 0.50 - add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Timeline view:
|
|
# CHECK-NEXT: 0123456789 0123456789
|
|
# CHECK-NEXT: Index 0123456789 0123456789 012
|
|
|
|
# CHECK: [0,0] DeeeeeeeeER . . . . . . . ld1 { v0.b }[0], [sp]
|
|
# CHECK-NEXT: [0,1] D========eeER . . . . . . . add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [1,0] D==========eeeeeeeeER . . . . . ld1 { v0.b }[0], [sp]
|
|
# CHECK-NEXT: [1,1] D==================eeER . . . . . add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [2,0] D====================eeeeeeeeER . . . ld1 { v0.b }[0], [sp]
|
|
# CHECK-NEXT: [2,1] .D===========================eeER . . . add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: [3,0] .D=============================eeeeeeeeER . ld1 { v0.b }[0], [sp]
|
|
# CHECK-NEXT: [3,1] .D=====================================eeER add v0.16b, v0.16b, v0.16b
|
|
|
|
# CHECK: Average Wait times (based on the timeline view):
|
|
# CHECK-NEXT: [0]: Executions
|
|
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
|
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
|
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
|
|
|
# CHECK: [0] [1] [2] [3]
|
|
# CHECK-NEXT: 0. 4 15.8 0.3 0.0 ld1 { v0.b }[0], [sp]
|
|
# CHECK-NEXT: 1. 4 23.5 0.0 0.0 add v0.16b, v0.16b, v0.16b
|
|
# CHECK-NEXT: 8 19.6 0.1 0.0 <total>
|