derek.holloway
7502bf64a4
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261 lines
16 KiB
ArmAsm
261 lines
16 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s
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# Two ALUs without dependency can be dispatched in the same cycle.
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add a0, a0, a0
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sub a1, a1, a1
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# Otherwise, they can't be dispatched in the same cycle.
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addw a0, a0, a0
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subw a0, a0, a0
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// ALU and Shift
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slli a0, a0, 4
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slliw a0, a0, 4
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srl a0, a0, a0
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srlw a0, a0, a0
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// MDU
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mul a0, a0, a0
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mulw a0, a0, a0
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div a0, a0, a0
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divw a0, a0, a0
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// Memory
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lb a0, 4(a1)
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lh a0, 4(a1)
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lw a0, 4(a1)
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ld a0, 4(a1)
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flw fa0, 4(a1)
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fld fa0, 4(a1)
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sb a0, 4(a1)
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sh a0, 4(a1)
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sw a0, 4(a1)
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sd a0, 4(a1)
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// Atomic Memory
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amoswap.w a0, a1, (a0)
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amoswap.d a0, a1, (a0)
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lr.w a0, (a0)
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lr.d a0, (a0)
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sc.w a0, a1, (a0)
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sc.d a0, a1, (a0)
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// CSR
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csrrw a0, mstatus, zero
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// Bitmanip
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sh1add a0, a0, a0
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sh1add.uw a0, a0, a0
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rori a0, a0, 4
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roriw a0, a0, 4
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rol a0, a0, a0
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rolw a0, a0, a0
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clz a0, a0
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clzw a0, a0
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clmul a0, a0, a0
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bclri a0, a0, 4
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bclr a0, a0, a0
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bexti a0, a0, 4
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bext a0, a0, a0
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 42
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# CHECK-NEXT: Total Cycles: 158
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# CHECK-NEXT: Total uOps: 42
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.27
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# CHECK-NEXT: IPC: 0.27
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# CHECK-NEXT: Block RThroughput: 80.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 1 0.50 add a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 sub a1, a1, a1
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# CHECK-NEXT: 1 1 0.50 addw a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 subw a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 slli a0, a0, 4
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# CHECK-NEXT: 1 1 0.50 slliw a0, a0, 4
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# CHECK-NEXT: 1 1 0.50 srl a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 srlw a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 mul a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 mulw a0, a0, a0
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# CHECK-NEXT: 1 39 39.00 div a0, a0, a0
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# CHECK-NEXT: 1 39 39.00 divw a0, a0, a0
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# CHECK-NEXT: 1 5 1.00 * lb a0, 4(a1)
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# CHECK-NEXT: 1 5 1.00 * lh a0, 4(a1)
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# CHECK-NEXT: 1 3 1.00 * lw a0, 4(a1)
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# CHECK-NEXT: 1 3 1.00 * ld a0, 4(a1)
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# CHECK-NEXT: 1 3 1.00 * flw fa0, 4(a1)
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# CHECK-NEXT: 1 3 1.00 * fld fa0, 4(a1)
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# CHECK-NEXT: 1 1 1.00 * sb a0, 4(a1)
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# CHECK-NEXT: 1 1 1.00 * sh a0, 4(a1)
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# CHECK-NEXT: 1 1 1.00 * sw a0, 4(a1)
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# CHECK-NEXT: 1 1 1.00 * sd a0, 4(a1)
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# CHECK-NEXT: 1 9 1.00 * * amoswap.w a0, a1, (a0)
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# CHECK-NEXT: 1 9 1.00 * * amoswap.d a0, a1, (a0)
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# CHECK-NEXT: 1 9 1.00 * lr.w a0, (a0)
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# CHECK-NEXT: 1 9 1.00 * lr.d a0, (a0)
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# CHECK-NEXT: 1 3 1.00 * sc.w a0, a1, (a0)
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# CHECK-NEXT: 1 3 1.00 * sc.d a0, a1, (a0)
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# CHECK-NEXT: 1 1 1.00 U csrrw a0, mstatus, zero
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# CHECK-NEXT: 1 1 0.50 sh1add a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 sh1add.uw a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 rori a0, a0, 4
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# CHECK-NEXT: 1 1 0.50 roriw a0, a0, 4
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# CHECK-NEXT: 1 1 0.50 rol a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 rolw a0, a0, a0
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# CHECK-NEXT: 1 3 0.50 clz a0, a0
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# CHECK-NEXT: 1 3 0.50 clzw a0, a0
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# CHECK-NEXT: 1 3 0.50 clmul a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 bclri a0, a0, 4
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# CHECK-NEXT: 1 1 0.50 bclr a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 bexti a0, a0, 4
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# CHECK-NEXT: 1 1 0.50 bext a0, a0, a0
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# CHECK: Resources:
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# CHECK-NEXT: [0.0] - Andes45ALU
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# CHECK-NEXT: [0.1] - Andes45ALU
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# CHECK-NEXT: [1] - Andes45CSR
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# CHECK-NEXT: [2] - Andes45FDIV
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# CHECK-NEXT: [3] - Andes45FMAC
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# CHECK-NEXT: [4] - Andes45FMISC
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# CHECK-NEXT: [5] - Andes45FMV
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# CHECK-NEXT: [6] - Andes45LSU
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# CHECK-NEXT: [7] - Andes45MDU
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# CHECK-NEXT: [8] - Andes45VALU
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# CHECK-NEXT: [9] - Andes45VDIV
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# CHECK-NEXT: [10] - Andes45VFDIV
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# CHECK-NEXT: [11] - Andes45VFMIS
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# CHECK-NEXT: [12] - Andes45VLSU
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# CHECK-NEXT: [13] - Andes45VMAC
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# CHECK-NEXT: [14] - Andes45VMASK
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# CHECK-NEXT: [15] - Andes45VPERMUT
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
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# CHECK-NEXT: 10.00 11.00 1.00 - - - - 16.00 80.00 - - - - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - add a0, a0, a0
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - sub a1, a1, a1
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - addw a0, a0, a0
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - subw a0, a0, a0
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - slli a0, a0, 4
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - slliw a0, a0, 4
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - srl a0, a0, a0
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - srlw a0, a0, a0
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# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - mul a0, a0, a0
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# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - mulw a0, a0, a0
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# CHECK-NEXT: - - - - - - - - 39.00 - - - - - - - - div a0, a0, a0
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# CHECK-NEXT: - - - - - - - - 39.00 - - - - - - - - divw a0, a0, a0
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lb a0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lh a0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lw a0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - ld a0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - flw fa0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - fld fa0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sb a0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sh a0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sw a0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sd a0, 4(a1)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - amoswap.w a0, a1, (a0)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - amoswap.d a0, a1, (a0)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lr.w a0, (a0)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lr.d a0, (a0)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sc.w a0, a1, (a0)
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# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sc.d a0, a1, (a0)
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - csrrw a0, mstatus, zero
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - sh1add a0, a0, a0
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - sh1add.uw a0, a0, a0
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - rori a0, a0, 4
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - roriw a0, a0, 4
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - rol a0, a0, a0
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - rolw a0, a0, a0
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - clz a0, a0
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - clzw a0, a0
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - clmul a0, a0, a0
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - bclri a0, a0, 4
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - bclr a0, a0, a0
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - bexti a0, a0, 4
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - bext a0, a0, a0
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# CHECK: Timeline view:
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# CHECK-NEXT: 0123456789 0123456789 012
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# CHECK-NEXT: Index 0123456789 0123456789 0123456789
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# CHECK: [0,0] DE . . . . . . . . . . . add a0, a0, a0
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# CHECK-NEXT: [0,1] DE . . . . . . . . . . . sub a1, a1, a1
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# CHECK-NEXT: [0,2] .DE . . . . . . . . . . . addw a0, a0, a0
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# CHECK-NEXT: [0,3] . DE . . . . . . . . . . . subw a0, a0, a0
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# CHECK-NEXT: [0,4] . DE. . . . . . . . . . . slli a0, a0, 4
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# CHECK-NEXT: [0,5] . DE . . . . . . . . . . slliw a0, a0, 4
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# CHECK-NEXT: [0,6] . DE . . . . . . . . . . srl a0, a0, a0
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# CHECK-NEXT: [0,7] . .DE . . . . . . . . . . srlw a0, a0, a0
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# CHECK-NEXT: [0,8] . . DeeE . . . . . . . . . mul a0, a0, a0
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# CHECK-NEXT: [0,9] . . DeeE . . . . . . . . . mulw a0, a0, a0
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# CHECK-NEXT: [0,10] . . . DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE div a0, a0, a0
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# CHECK-NEXT: Truncated display due to cycle limit
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 0.0 0.0 0.0 add a0, a0, a0
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# CHECK-NEXT: 1. 1 0.0 0.0 0.0 sub a1, a1, a1
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# CHECK-NEXT: 2. 1 0.0 0.0 0.0 addw a0, a0, a0
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# CHECK-NEXT: 3. 1 0.0 0.0 0.0 subw a0, a0, a0
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# CHECK-NEXT: 4. 1 0.0 0.0 0.0 slli a0, a0, 4
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# CHECK-NEXT: 5. 1 0.0 0.0 0.0 slliw a0, a0, 4
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# CHECK-NEXT: 6. 1 0.0 0.0 0.0 srl a0, a0, a0
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# CHECK-NEXT: 7. 1 0.0 0.0 0.0 srlw a0, a0, a0
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# CHECK-NEXT: 8. 1 0.0 0.0 0.0 mul a0, a0, a0
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# CHECK-NEXT: 9. 1 0.0 0.0 0.0 mulw a0, a0, a0
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# CHECK-NEXT: 10. 1 0.0 0.0 0.0 div a0, a0, a0
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# CHECK-NEXT: 11. 1 0.0 0.0 0.0 divw a0, a0, a0
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# CHECK-NEXT: 12. 1 0.0 0.0 0.0 lb a0, 4(a1)
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# CHECK-NEXT: 13. 1 0.0 0.0 0.0 lh a0, 4(a1)
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# CHECK-NEXT: 14. 1 0.0 0.0 0.0 lw a0, 4(a1)
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# CHECK-NEXT: 15. 1 0.0 0.0 0.0 ld a0, 4(a1)
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# CHECK-NEXT: 16. 1 0.0 0.0 0.0 flw fa0, 4(a1)
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# CHECK-NEXT: 17. 1 0.0 0.0 0.0 fld fa0, 4(a1)
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# CHECK-NEXT: 18. 1 0.0 0.0 0.0 sb a0, 4(a1)
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# CHECK-NEXT: 19. 1 0.0 0.0 0.0 sh a0, 4(a1)
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# CHECK-NEXT: 20. 1 0.0 0.0 0.0 sw a0, 4(a1)
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# CHECK-NEXT: 21. 1 0.0 0.0 0.0 sd a0, 4(a1)
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# CHECK-NEXT: 22. 1 0.0 0.0 0.0 amoswap.w a0, a1, (a0)
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# CHECK-NEXT: 23. 1 0.0 0.0 0.0 amoswap.d a0, a1, (a0)
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# CHECK-NEXT: 24. 1 0.0 0.0 0.0 lr.w a0, (a0)
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# CHECK-NEXT: 25. 1 0.0 0.0 0.0 lr.d a0, (a0)
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# CHECK-NEXT: 26. 1 0.0 0.0 0.0 sc.w a0, a1, (a0)
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# CHECK-NEXT: 27. 1 0.0 0.0 0.0 sc.d a0, a1, (a0)
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# CHECK-NEXT: 28. 1 0.0 0.0 0.0 csrrw a0, mstatus, zero
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# CHECK-NEXT: 29. 1 0.0 0.0 0.0 sh1add a0, a0, a0
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# CHECK-NEXT: 30. 1 0.0 0.0 0.0 sh1add.uw a0, a0, a0
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# CHECK-NEXT: 31. 1 0.0 0.0 0.0 rori a0, a0, 4
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# CHECK-NEXT: 32. 1 0.0 0.0 0.0 roriw a0, a0, 4
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# CHECK-NEXT: 33. 1 0.0 0.0 0.0 rol a0, a0, a0
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# CHECK-NEXT: 34. 1 0.0 0.0 0.0 rolw a0, a0, a0
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# CHECK-NEXT: 35. 1 0.0 0.0 0.0 clz a0, a0
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# CHECK-NEXT: 36. 1 0.0 0.0 0.0 clzw a0, a0
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# CHECK-NEXT: 37. 1 0.0 0.0 0.0 clmul a0, a0, a0
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# CHECK-NEXT: 38. 1 0.0 0.0 0.0 bclri a0, a0, 4
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# CHECK-NEXT: 39. 1 0.0 0.0 0.0 bclr a0, a0, a0
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# CHECK-NEXT: 40. 1 0.0 0.0 0.0 bexti a0, a0, 4
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# CHECK-NEXT: 41. 1 0.0 0.0 0.0 bext a0, a0, a0
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# CHECK-NEXT: 42 0.0 0.0 0.0 <total>
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