derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
4346 lines
481 KiB
ArmAsm
4346 lines
481 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
|
# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
|
|
|
|
# Bitwise and logical operations
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vand.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vand.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vand.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vand.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vand.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vand.vi v8, v8, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vor.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vor.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vor.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vor.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vor.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vor.vi v8, v8, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vxor.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vxor.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vxor.vi v8, v8, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnsra.wv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnsra.wx v8, v16, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnsra.wi v8, v16, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnsrl.wv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnsrl.wx v8, v16, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnsrl.wi v8, v16, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnclipu.wi v8, v16, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnclipu.wv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnclipu.wx v8, v16, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnclip.wi v8, v16, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnclip.wv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnclip.wx v8, v16, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsll.vi v8, v8, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsll.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsll.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsra.vi v8, v8, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsra.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsra.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsrl.vi v8, v8, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsrl.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsrl.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vssra.vi v8, v8, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vssra.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vssra.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vssrl.vi v8, v8, 12
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vssrl.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vssrl.vx v8, v8, x30
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0] - Andes45ALU:2
|
|
# CHECK-NEXT: [1] - Andes45CSR:1
|
|
# CHECK-NEXT: [2] - Andes45FDIV:1
|
|
# CHECK-NEXT: [3] - Andes45FMAC:1
|
|
# CHECK-NEXT: [4] - Andes45FMISC:1
|
|
# CHECK-NEXT: [5] - Andes45FMV:1
|
|
# CHECK-NEXT: [6] - Andes45LSU:1
|
|
# CHECK-NEXT: [7] - Andes45MDU:1
|
|
# CHECK-NEXT: [8] - Andes45VALU:1
|
|
# CHECK-NEXT: [9] - Andes45VDIV:1
|
|
# CHECK-NEXT: [10] - Andes45VFDIV:1
|
|
# CHECK-NEXT: [11] - Andes45VFMIS:1
|
|
# CHECK-NEXT: [12] - Andes45VLSU:1
|
|
# CHECK-NEXT: [13] - Andes45VMAC:1
|
|
# CHECK-NEXT: [14] - Andes45VMASK:1
|
|
# CHECK-NEXT: [15] - Andes45VPERMUT:1
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
# CHECK-NEXT: [7]: Bypass Latency
|
|
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
|
|
# CHECK-NEXT: [9]: LLVM Opcode Name
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VV vand.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VX vand.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VI vand.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VV vor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VX vor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VI vor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VV vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VX vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VI vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WV vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WX vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WI vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WV vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WX vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WI vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WI vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WV vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNCLIP_WX vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VI vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VV vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VX vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VI vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VV vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VX vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VI vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VV vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VX vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VI vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VV vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRA_VX vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VI vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VV vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSSRL_VX vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSSRL_VX vssrl.vx v8, v8, t5
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - Andes45ALU
|
|
# CHECK-NEXT: [0.1] - Andes45ALU
|
|
# CHECK-NEXT: [1] - Andes45CSR
|
|
# CHECK-NEXT: [2] - Andes45FDIV
|
|
# CHECK-NEXT: [3] - Andes45FMAC
|
|
# CHECK-NEXT: [4] - Andes45FMISC
|
|
# CHECK-NEXT: [5] - Andes45FMV
|
|
# CHECK-NEXT: [6] - Andes45LSU
|
|
# CHECK-NEXT: [7] - Andes45MDU
|
|
# CHECK-NEXT: [8] - Andes45VALU
|
|
# CHECK-NEXT: [9] - Andes45VDIV
|
|
# CHECK-NEXT: [10] - Andes45VFDIV
|
|
# CHECK-NEXT: [11] - Andes45VFMIS
|
|
# CHECK-NEXT: [12] - Andes45VLSU
|
|
# CHECK-NEXT: [13] - Andes45VMAC
|
|
# CHECK-NEXT: [14] - Andes45VMASK
|
|
# CHECK-NEXT: [15] - Andes45VPERMUT
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
|
|
# CHECK-NEXT: - - 708.00 - - - - - - 2160.00 - - - - - - -
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclipu.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wi v8, v16, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnclip.wx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssra.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vi v8, v8, 12
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vssrl.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vssrl.vx v8, v8, t5
|