derek.holloway
7502bf64a4
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2203 lines
244 KiB
ArmAsm
2203 lines
244 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
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# Fused multiply-add operations
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vsetvli x28, x0, e8, mf2, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e8, mf4, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e8, mf8, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e8, m1, tu, mu
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vmacc.vv v8, v8, v8
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|
vsetvli x28, x0, e8, m2, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e8, m4, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e8, m8, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e16, mf2, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e16, mf4, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e16, m1, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e16, m2, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e16, m4, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e16, m8, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e32, mf2, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e32, m1, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e32, m2, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e32, m4, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e32, m8, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e64, m1, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e64, m2, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e64, m4, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e64, m8, tu, mu
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vmacc.vv v8, v8, v8
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vsetvli x28, x0, e8, mf2, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e8, mf4, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e8, mf8, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e8, m1, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e8, m2, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e8, m4, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e8, m8, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e16, mf2, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e16, mf4, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e16, m1, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e16, m2, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e16, m4, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e16, m8, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e32, mf2, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e32, m1, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e32, m2, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e32, m4, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e32, m8, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e64, m1, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e64, m2, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e64, m4, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e64, m8, tu, mu
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vmacc.vx v8, x8, v8
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vsetvli x28, x0, e8, mf2, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e8, mf4, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e8, mf8, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e8, m1, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e8, m2, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e8, m4, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e8, m8, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e16, mf2, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e16, mf4, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e16, m1, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e16, m2, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e16, m4, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e16, m8, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e32, mf2, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e32, m1, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e32, m2, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e32, m4, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e32, m8, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e64, m1, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e64, m2, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e64, m4, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e64, m8, tu, mu
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vmadd.vv v8, v8, v8
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vsetvli x28, x0, e8, mf2, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e8, mf4, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e8, mf8, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e8, m1, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e8, m2, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e8, m4, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e8, m8, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e16, mf2, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e16, mf4, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e16, m1, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e16, m2, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e16, m4, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e16, m8, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e32, mf2, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e32, m1, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e32, m2, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e32, m4, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e32, m8, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e64, m1, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e64, m2, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e64, m4, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e64, m8, tu, mu
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vmadd.vx v8, x8, v8
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vsetvli x28, x0, e8, mf2, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e8, mf4, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e8, mf8, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e8, m1, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e8, m2, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e8, m4, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e8, m8, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e16, mf2, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e16, mf4, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e16, m1, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e16, m2, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e16, m4, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e16, m8, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e32, mf2, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e32, m1, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e32, m2, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e32, m4, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e32, m8, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e64, m1, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e64, m2, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e64, m4, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e64, m8, tu, mu
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vnmsac.vv v8, v8, v8
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vsetvli x28, x0, e8, mf2, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e8, mf4, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e8, mf8, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e8, m1, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e8, m2, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e8, m4, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e8, m8, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e16, mf2, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e16, mf4, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e16, m1, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e16, m2, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e16, m4, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e16, m8, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e32, mf2, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e32, m1, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e32, m2, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e32, m4, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e32, m8, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e64, m1, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e64, m2, tu, mu
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|
vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e64, m4, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e64, m8, tu, mu
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vnmsac.vx v8, x8, v8
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vsetvli x28, x0, e8, mf2, tu, mu
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vnmsub.vv v8, v8, v8
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vsetvli x28, x0, e8, mf4, tu, mu
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vnmsub.vv v8, v8, v8
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|
vsetvli x28, x0, e8, mf8, tu, mu
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|
vnmsub.vv v8, v8, v8
|
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vsetvli x28, x0, e8, m1, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
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vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vnmsub.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vnmsub.vx v8, x8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmaccu.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmaccu.vx v8, x16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmacc.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmacc.vx v8, x16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmaccsu.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmaccsu.vx v8, x16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmaccus.vx v8, x16, v24
|
|
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vfwmacc.vf v8, f16, v24
|
|
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vfwmacc.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vfwmsac.vf v8, f16, v24
|
|
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vfwmsac.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vfwnmacc.vf v8, f16, v24
|
|
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vfwnmacc.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vfwnmsac.vf v8, f16, v24
|
|
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vfwnmsac.vv v8, v16, v24
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0] - Andes45ALU:2
|
|
# CHECK-NEXT: [1] - Andes45CSR:1
|
|
# CHECK-NEXT: [2] - Andes45FDIV:1
|
|
# CHECK-NEXT: [3] - Andes45FMAC:1
|
|
# CHECK-NEXT: [4] - Andes45FMISC:1
|
|
# CHECK-NEXT: [5] - Andes45FMV:1
|
|
# CHECK-NEXT: [6] - Andes45LSU:1
|
|
# CHECK-NEXT: [7] - Andes45MDU:1
|
|
# CHECK-NEXT: [8] - Andes45VALU:1
|
|
# CHECK-NEXT: [9] - Andes45VDIV:1
|
|
# CHECK-NEXT: [10] - Andes45VFDIV:1
|
|
# CHECK-NEXT: [11] - Andes45VFMIS:1
|
|
# CHECK-NEXT: [12] - Andes45VLSU:1
|
|
# CHECK-NEXT: [13] - Andes45VMAC:1
|
|
# CHECK-NEXT: [14] - Andes45VMASK:1
|
|
# CHECK-NEXT: [15] - Andes45VPERMUT:1
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
# CHECK-NEXT: [7]: Bypass Latency
|
|
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
|
|
# CHECK-NEXT: [9]: LLVM Opcode Name
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VV vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VX vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VV vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VX vmadd.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VV vnmsac.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VX vnmsac.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VV vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VX vnmsub.vx v8, s0, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VV vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VX vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWMACC_VV vfwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 6 1.00 6 Andes45VMAC VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 6 2.00 6 Andes45VMAC[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 6 4.00 6 Andes45VMAC[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 6 8.00 6 Andes45VMAC[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - Andes45ALU
|
|
# CHECK-NEXT: [0.1] - Andes45ALU
|
|
# CHECK-NEXT: [1] - Andes45CSR
|
|
# CHECK-NEXT: [2] - Andes45FDIV
|
|
# CHECK-NEXT: [3] - Andes45FMAC
|
|
# CHECK-NEXT: [4] - Andes45FMISC
|
|
# CHECK-NEXT: [5] - Andes45FMV
|
|
# CHECK-NEXT: [6] - Andes45LSU
|
|
# CHECK-NEXT: [7] - Andes45MDU
|
|
# CHECK-NEXT: [8] - Andes45VALU
|
|
# CHECK-NEXT: [9] - Andes45VDIV
|
|
# CHECK-NEXT: [10] - Andes45VFDIV
|
|
# CHECK-NEXT: [11] - Andes45VFMIS
|
|
# CHECK-NEXT: [12] - Andes45VLSU
|
|
# CHECK-NEXT: [13] - Andes45VMAC
|
|
# CHECK-NEXT: [14] - Andes45VMASK
|
|
# CHECK-NEXT: [15] - Andes45VPERMUT
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
|
|
# CHECK-NEXT: - - 353.00 - - - - - - - - - - - 1112.00 - -
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vx v8, s0, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vv v8, v8, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vv v8, v8, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vv v8, v8, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vx v8, s0, v8
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vv v8, v16, v24
|
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmacc.vf v8, fa6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmacc.vf v8, fa6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmsac.vf v8, fa6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmsac.vf v8, fa6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmsac.vf v8, fa6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vfwmsac.vf v8, fa6, v24
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# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vfwmsac.vf v8, fa6, v24
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