derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
3002 lines
332 KiB
ArmAsm
3002 lines
332 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
|
# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s
|
|
|
|
# Multiplication and division operations
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vmul.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vmul.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vdiv.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vdiv.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vdivu.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vdivu.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vrem.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vrem.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vremu.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vremu.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vmulh.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vmulh.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vmulhu.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vmulhu.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vmulhsu.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vmulhsu.vx v8, v8, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmul.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmul.vx v8, v16, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmulu.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmulu.vx v8, v16, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmulsu.vv v8, v16, v24
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vwmulsu.vx v8, v16, x30
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsmul.vv v8, v8, v8
|
|
|
|
vsetvli x28, x0, e8, mf2, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf4, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, mf8, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m1, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m2, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m4, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e8, m8, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf2, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, mf4, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m1, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m2, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m4, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e16, m8, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, mf2, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m1, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m2, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m4, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e32, m8, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m1, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m2, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m4, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
vsetvli x28, x0, e64, m8, tu, mu
|
|
vsmul.vx v8, v8, x30
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0] - Andes45ALU:2
|
|
# CHECK-NEXT: [1] - Andes45CSR:1
|
|
# CHECK-NEXT: [2] - Andes45FDIV:1
|
|
# CHECK-NEXT: [3] - Andes45FMAC:1
|
|
# CHECK-NEXT: [4] - Andes45FMISC:1
|
|
# CHECK-NEXT: [5] - Andes45FMV:1
|
|
# CHECK-NEXT: [6] - Andes45LSU:1
|
|
# CHECK-NEXT: [7] - Andes45MDU:1
|
|
# CHECK-NEXT: [8] - Andes45VALU:1
|
|
# CHECK-NEXT: [9] - Andes45VDIV:1
|
|
# CHECK-NEXT: [10] - Andes45VFDIV:1
|
|
# CHECK-NEXT: [11] - Andes45VFMIS:1
|
|
# CHECK-NEXT: [12] - Andes45VLSU:1
|
|
# CHECK-NEXT: [13] - Andes45VMAC:1
|
|
# CHECK-NEXT: [14] - Andes45VMASK:1
|
|
# CHECK-NEXT: [15] - Andes45VPERMUT:1
|
|
|
|
# CHECK: Instruction Info:
|
|
# CHECK-NEXT: [1]: #uOps
|
|
# CHECK-NEXT: [2]: Latency
|
|
# CHECK-NEXT: [3]: RThroughput
|
|
# CHECK-NEXT: [4]: MayLoad
|
|
# CHECK-NEXT: [5]: MayStore
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
|
# CHECK-NEXT: [7]: Bypass Latency
|
|
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
|
|
# CHECK-NEXT: [9]: LLVM Opcode Name
|
|
|
|
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VV vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VX vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VDIV_VV vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VDIV_VX vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VDIVU_VV vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VDIVU_VX vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VREM_VV vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VREM_VX vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VREMU_VV vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VREMU_VX vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VV vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VX vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VV vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VX vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VV vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VX vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VV vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VX vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VSMUL_VV vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VSMUL_VX vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VSMUL_VX vsmul.vx v8, v8, t5
|
|
|
|
# CHECK: Resources:
|
|
# CHECK-NEXT: [0.0] - Andes45ALU
|
|
# CHECK-NEXT: [0.1] - Andes45ALU
|
|
# CHECK-NEXT: [1] - Andes45CSR
|
|
# CHECK-NEXT: [2] - Andes45FDIV
|
|
# CHECK-NEXT: [3] - Andes45FMAC
|
|
# CHECK-NEXT: [4] - Andes45FMISC
|
|
# CHECK-NEXT: [5] - Andes45FMV
|
|
# CHECK-NEXT: [6] - Andes45LSU
|
|
# CHECK-NEXT: [7] - Andes45MDU
|
|
# CHECK-NEXT: [8] - Andes45VALU
|
|
# CHECK-NEXT: [9] - Andes45VDIV
|
|
# CHECK-NEXT: [10] - Andes45VFDIV
|
|
# CHECK-NEXT: [11] - Andes45VFMIS
|
|
# CHECK-NEXT: [12] - Andes45VLSU
|
|
# CHECK-NEXT: [13] - Andes45VMAC
|
|
# CHECK-NEXT: [14] - Andes45VMASK
|
|
# CHECK-NEXT: [15] - Andes45VPERMUT
|
|
|
|
# CHECK: Resource pressure per iteration:
|
|
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
|
|
# CHECK-NEXT: - - 486.00 - - - - - - - 16336.00 - - - 948.00 - -
|
|
|
|
# CHECK: Resource pressure by instruction:
|
|
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions:
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vdiv.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vdiv.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vdivu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vdivu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vrem.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vrem.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vremu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vremu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vv v8, v16, v24
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vx v8, v16, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vv v8, v8, v8
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vsmul.vx v8, v8, t5
|
|
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
|
|
# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vsmul.vx v8, v8, t5
|