derek.holloway
7502bf64a4
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416 lines
19 KiB
ArmAsm
416 lines
19 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables < %s | FileCheck %s -check-prefixes=ALL,ISN
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables -show-barriers < %s | FileCheck %s -check-prefixes=ALL,ISNB
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISNE
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables -show-barriers -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISNBE
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=normal < %s | FileCheck %s -check-prefixes=ALL,ISN
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=normal -show-barriers < %s | FileCheck %s -check-prefixes=ALL,ISNB
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=normal -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISNE
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=normal -show-barriers -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISNBE
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=none < %s | FileCheck %s -check-prefixes=ALL
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=none -show-barriers < %s | FileCheck %s -check-prefixes=ALL,NISB
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=none -show-encoding < %s | FileCheck %s -check-prefixes=ALL,NISE
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=none -show-barriers -show-encoding < %s | FileCheck %s -check-prefixes=ALL,NISBE
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full < %s | FileCheck %s -check-prefixes=ALL,ISF
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full -show-barriers < %s | FileCheck %s -check-prefixes=ALL,ISFB
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISFE
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# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full -show-barriers -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISFBE
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vsetvli a3, a2, e16, m1, tu, mu // Comment
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vlm.v v4, (a1)
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# NISB: Iterations: 100
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# NISB-NEXT: Instructions: 200
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# NISB-NEXT: Total Cycles: 404
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# NISB-NEXT: Total uOps: 200
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# NISBE: Iterations: 100
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# NISBE-NEXT: Instructions: 200
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# NISBE-NEXT: Total Cycles: 404
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# NISBE-NEXT: Total uOps: 200
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# NISE: Iterations: 100
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# NISE-NEXT: Instructions: 200
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# NISE-NEXT: Total Cycles: 404
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# NISE-NEXT: Total uOps: 200
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# ISF: Resources:
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# ISF-NEXT: [0] - VLEN512SiFive7FDiv:1
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# ISF-NEXT: [1] - VLEN512SiFive7IDiv:1
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# ISF-NEXT: [2] - VLEN512SiFive7PipeA:1
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# ISF-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
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# ISF-NEXT: [4] - VLEN512SiFive7PipeB:1
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# ISF-NEXT: [5] - VLEN512SiFive7VA1:1
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# ISF-NEXT: [6] - VLEN512SiFive7VCQ:1
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# ISF-NEXT: [7] - VLEN512SiFive7VL:1
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# ISF-NEXT: [8] - VLEN512SiFive7VS:1
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# ISFB: Resources:
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# ISFB-NEXT: [0] - VLEN512SiFive7FDiv:1
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# ISFB-NEXT: [1] - VLEN512SiFive7IDiv:1
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# ISFB-NEXT: [2] - VLEN512SiFive7PipeA:1
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# ISFB-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
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# ISFB-NEXT: [4] - VLEN512SiFive7PipeB:1
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# ISFB-NEXT: [5] - VLEN512SiFive7VA1:1
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# ISFB-NEXT: [6] - VLEN512SiFive7VCQ:1
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# ISFB-NEXT: [7] - VLEN512SiFive7VL:1
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# ISFB-NEXT: [8] - VLEN512SiFive7VS:1
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# ISFBE: Resources:
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# ISFBE-NEXT: [0] - VLEN512SiFive7FDiv:1
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# ISFBE-NEXT: [1] - VLEN512SiFive7IDiv:1
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# ISFBE-NEXT: [2] - VLEN512SiFive7PipeA:1
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# ISFBE-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
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# ISFBE-NEXT: [4] - VLEN512SiFive7PipeB:1
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# ISFBE-NEXT: [5] - VLEN512SiFive7VA1:1
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# ISFBE-NEXT: [6] - VLEN512SiFive7VCQ:1
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# ISFBE-NEXT: [7] - VLEN512SiFive7VL:1
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# ISFBE-NEXT: [8] - VLEN512SiFive7VS:1
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# ISFE: Resources:
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# ISFE-NEXT: [0] - VLEN512SiFive7FDiv:1
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# ISFE-NEXT: [1] - VLEN512SiFive7IDiv:1
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# ISFE-NEXT: [2] - VLEN512SiFive7PipeA:1
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# ISFE-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
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# ISFE-NEXT: [4] - VLEN512SiFive7PipeB:1
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# ISFE-NEXT: [5] - VLEN512SiFive7VA1:1
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# ISFE-NEXT: [6] - VLEN512SiFive7VCQ:1
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# ISFE-NEXT: [7] - VLEN512SiFive7VL:1
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# ISFE-NEXT: [8] - VLEN512SiFive7VS:1
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# ISN: Instruction Info:
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# ISN-NEXT: [1]: #uOps
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# ISN-NEXT: [2]: Latency
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# ISN-NEXT: [3]: RThroughput
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# ISN-NEXT: [4]: MayLoad
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# ISN-NEXT: [5]: MayStore
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# ISN-NEXT: [6]: HasSideEffects (U)
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# ISNB: Instruction Info:
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# ISNB-NEXT: [1]: #uOps
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# ISNB-NEXT: [2]: Latency
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# ISNB-NEXT: [3]: RThroughput
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# ISNB-NEXT: [4]: MayLoad
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# ISNB-NEXT: [5]: MayStore
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# ISNB-NEXT: [6]: HasSideEffects (U)
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# ISNB-NEXT: [7]: LoadBarrier
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# ISNB-NEXT: [8]: StoreBarrier
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# ISNBE: Instruction Info:
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# ISNBE-NEXT: [1]: #uOps
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# ISNBE-NEXT: [2]: Latency
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# ISNBE-NEXT: [3]: RThroughput
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# ISNBE-NEXT: [4]: MayLoad
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# ISNBE-NEXT: [5]: MayStore
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# ISNBE-NEXT: [6]: HasSideEffects (U)
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# ISNBE-NEXT: [7]: LoadBarrier
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# ISNBE-NEXT: [8]: StoreBarrier
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# ISNBE-NEXT: [9]: Encoding Size
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# ISNE: Instruction Info:
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# ISNE-NEXT: [1]: #uOps
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# ISNE-NEXT: [2]: Latency
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# ISNE-NEXT: [3]: RThroughput
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# ISNE-NEXT: [4]: MayLoad
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# ISNE-NEXT: [5]: MayStore
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# ISNE-NEXT: [6]: HasSideEffects (U)
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# ISNE-NEXT: [7]: Encoding Size
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# NISB: Dispatch Width: 2
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# NISB-NEXT: uOps Per Cycle: 0.50
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# NISB-NEXT: IPC: 0.50
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# NISB-NEXT: Block RThroughput: 3.0
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# NISBE: Dispatch Width: 2
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# NISBE-NEXT: uOps Per Cycle: 0.50
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# NISBE-NEXT: IPC: 0.50
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# NISBE-NEXT: Block RThroughput: 3.0
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# NISE: Dispatch Width: 2
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# NISE-NEXT: uOps Per Cycle: 0.50
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# NISE-NEXT: IPC: 0.50
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# NISE-NEXT: Block RThroughput: 3.0
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# ISF: Instruction Info:
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# ISF-NEXT: [1]: #uOps
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# ISF-NEXT: [2]: Latency
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# ISF-NEXT: [3]: RThroughput
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# ISF-NEXT: [4]: MayLoad
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# ISF-NEXT: [5]: MayStore
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# ISF-NEXT: [6]: HasSideEffects (U)
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# ISF-NEXT: [7]: Bypass Latency
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# ISF-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# ISF-NEXT: [9]: LLVM Opcode Name
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# ISFB: Instruction Info:
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# ISFB-NEXT: [1]: #uOps
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# ISFB-NEXT: [2]: Latency
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# ISFB-NEXT: [3]: RThroughput
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# ISFB-NEXT: [4]: MayLoad
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# ISFB-NEXT: [5]: MayStore
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# ISFB-NEXT: [6]: HasSideEffects (U)
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# ISFB-NEXT: [7]: Bypass Latency
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# ISFB-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# ISFB-NEXT: [9]: LLVM Opcode Name
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# ISFB-NEXT: [10]: LoadBarrier
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# ISFB-NEXT: [11]: StoreBarrier
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# ISFBE: Instruction Info:
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# ISFBE-NEXT: [1]: #uOps
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# ISFBE-NEXT: [2]: Latency
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# ISFBE-NEXT: [3]: RThroughput
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# ISFBE-NEXT: [4]: MayLoad
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# ISFBE-NEXT: [5]: MayStore
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# ISFBE-NEXT: [6]: HasSideEffects (U)
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# ISFBE-NEXT: [7]: Bypass Latency
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# ISFBE-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# ISFBE-NEXT: [9]: LLVM Opcode Name
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# ISFBE-NEXT: [10]: LoadBarrier
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# ISFBE-NEXT: [11]: StoreBarrier
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# ISFBE-NEXT: [12]: Encoding Size
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# ISFE: Instruction Info:
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# ISFE-NEXT: [1]: #uOps
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# ISFE-NEXT: [2]: Latency
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# ISFE-NEXT: [3]: RThroughput
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# ISFE-NEXT: [4]: MayLoad
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# ISFE-NEXT: [5]: MayStore
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# ISFE-NEXT: [6]: HasSideEffects (U)
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# ISFE-NEXT: [7]: Bypass Latency
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# ISFE-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# ISFE-NEXT: [9]: LLVM Opcode Name
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# ISFE-NEXT: [10]: Encoding Size
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# ISN: [1] [2] [3] [4] [5] [6] Instructions:
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# ISN-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
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# ISN-NEXT: 1 4 2.00 * vlm.v v4, (a1)
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# NISB: Instruction Info:
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# NISB-NEXT: [1]: #uOps
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# NISB-NEXT: [2]: Latency
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# NISB-NEXT: [3]: RThroughput
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# NISB-NEXT: [4]: MayLoad
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# NISB-NEXT: [5]: MayStore
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# NISB-NEXT: [6]: HasSideEffects (U)
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# NISB-NEXT: [7]: LoadBarrier
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# NISB-NEXT: [8]: StoreBarrier
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# NISBE: Instruction Info:
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# NISBE-NEXT: [1]: #uOps
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# NISBE-NEXT: [2]: Latency
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# NISBE-NEXT: [3]: RThroughput
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# NISBE-NEXT: [4]: MayLoad
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# NISBE-NEXT: [5]: MayStore
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# NISBE-NEXT: [6]: HasSideEffects (U)
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# NISBE-NEXT: [7]: LoadBarrier
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# NISBE-NEXT: [8]: StoreBarrier
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# NISBE-NEXT: [9]: Encoding Size
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# NISE: Instruction Info:
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# NISE-NEXT: [1]: #uOps
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# NISE-NEXT: [2]: Latency
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# NISE-NEXT: [3]: RThroughput
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# NISE-NEXT: [4]: MayLoad
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# NISE-NEXT: [5]: MayStore
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# NISE-NEXT: [6]: HasSideEffects (U)
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# NISE-NEXT: [7]: Encoding Size
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# ISF: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# ISF-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a3, a2, e16, m1, tu, mu // Comment
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# ISF-NEXT: 1 4 2.00 * 4 VLEN512SiFive7VCQ,VLEN512SiFive7VL[1,3] VLM_V vlm.v v4, (a1)
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# ISFB: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
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# ISFB-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a3, a2, e16, m1, tu, mu // Comment
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# ISFB-NEXT: 1 4 2.00 * 4 VLEN512SiFive7VCQ,VLEN512SiFive7VL[1,3] VLM_V vlm.v v4, (a1)
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# ISFBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Encodings: Instructions:
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# ISFBE-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu // Comment
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# ISFBE-NEXT: 1 4 2.00 * 4 VLEN512SiFive7VCQ,VLEN512SiFive7VL[1,3] VLM_V 4 07 82 b5 02 vlm.v v4, (a1)
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# ISFE: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] Encodings: Instructions:
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# ISFE-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu // Comment
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# ISFE-NEXT: 1 4 2.00 * 4 VLEN512SiFive7VCQ,VLEN512SiFive7VL[1,3] VLM_V 4 07 82 b5 02 vlm.v v4, (a1)
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# ISNB: [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
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# ISNB-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
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# ISNB-NEXT: 1 4 2.00 * vlm.v v4, (a1)
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# ISNBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] Encodings: Instructions:
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# ISNBE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
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# ISNBE-NEXT: 1 4 2.00 * 4 07 82 b5 02 vlm.v v4, (a1)
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# ISNE: [1] [2] [3] [4] [5] [6] [7] Encodings: Instructions:
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# ISNE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
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# ISNE-NEXT: 1 4 2.00 * 4 07 82 b5 02 vlm.v v4, (a1)
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# NISB: [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
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# NISB-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
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# NISB-NEXT: 1 4 2.00 * vlm.v v4, (a1)
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# NISBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] Encodings: Instructions:
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# NISBE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
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# NISBE-NEXT: 1 4 2.00 * 4 07 82 b5 02 vlm.v v4, (a1)
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# NISE: [1] [2] [3] [4] [5] [6] [7] Encodings: Instructions:
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# NISE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
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# NISE-NEXT: 1 4 2.00 * 4 07 82 b5 02 vlm.v v4, (a1)
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# ISN: Resources:
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# ISN-NEXT: [0] - VLEN512SiFive7FDiv
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# ISN-NEXT: [1] - VLEN512SiFive7IDiv
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# ISN-NEXT: [2] - VLEN512SiFive7PipeA
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# ISN-NEXT: [3] - VLEN512SiFive7PipeB
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# ISN-NEXT: [4] - VLEN512SiFive7VA1
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# ISN-NEXT: [5] - VLEN512SiFive7VCQ
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# ISN-NEXT: [6] - VLEN512SiFive7VL
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# ISN-NEXT: [7] - VLEN512SiFive7VS
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# ISF: Resources:
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# ISF-NEXT: [0] - VLEN512SiFive7FDiv
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# ISF-NEXT: [1] - VLEN512SiFive7IDiv
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# ISF-NEXT: [2] - VLEN512SiFive7PipeA
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# ISF-NEXT: [3] - VLEN512SiFive7PipeB
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# ISF-NEXT: [4] - VLEN512SiFive7VA1
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# ISF-NEXT: [5] - VLEN512SiFive7VCQ
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# ISF-NEXT: [6] - VLEN512SiFive7VL
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# ISF-NEXT: [7] - VLEN512SiFive7VS
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# ISFB: Resources:
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# ISFB-NEXT: [0] - VLEN512SiFive7FDiv
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# ISFB-NEXT: [1] - VLEN512SiFive7IDiv
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# ISFB-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# ISFB-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# ISFB-NEXT: [4] - VLEN512SiFive7VA1
|
|
# ISFB-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# ISFB-NEXT: [6] - VLEN512SiFive7VL
|
|
# ISFB-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# ISFBE: Resources:
|
|
# ISFBE-NEXT: [0] - VLEN512SiFive7FDiv
|
|
# ISFBE-NEXT: [1] - VLEN512SiFive7IDiv
|
|
# ISFBE-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# ISFBE-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# ISFBE-NEXT: [4] - VLEN512SiFive7VA1
|
|
# ISFBE-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# ISFBE-NEXT: [6] - VLEN512SiFive7VL
|
|
# ISFBE-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# ISFE: Resources:
|
|
# ISFE-NEXT: [0] - VLEN512SiFive7FDiv
|
|
# ISFE-NEXT: [1] - VLEN512SiFive7IDiv
|
|
# ISFE-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# ISFE-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# ISFE-NEXT: [4] - VLEN512SiFive7VA1
|
|
# ISFE-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# ISFE-NEXT: [6] - VLEN512SiFive7VL
|
|
# ISFE-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# ISNB: Resources:
|
|
# ISNB-NEXT: [0] - VLEN512SiFive7FDiv
|
|
# ISNB-NEXT: [1] - VLEN512SiFive7IDiv
|
|
# ISNB-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# ISNB-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# ISNB-NEXT: [4] - VLEN512SiFive7VA1
|
|
# ISNB-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# ISNB-NEXT: [6] - VLEN512SiFive7VL
|
|
# ISNB-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# ISNBE: Resources:
|
|
# ISNBE-NEXT: [0] - VLEN512SiFive7FDiv
|
|
# ISNBE-NEXT: [1] - VLEN512SiFive7IDiv
|
|
# ISNBE-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# ISNBE-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# ISNBE-NEXT: [4] - VLEN512SiFive7VA1
|
|
# ISNBE-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# ISNBE-NEXT: [6] - VLEN512SiFive7VL
|
|
# ISNBE-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# ISNE: Resources:
|
|
# ISNE-NEXT: [0] - VLEN512SiFive7FDiv
|
|
# ISNE-NEXT: [1] - VLEN512SiFive7IDiv
|
|
# ISNE-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# ISNE-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# ISNE-NEXT: [4] - VLEN512SiFive7VA1
|
|
# ISNE-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# ISNE-NEXT: [6] - VLEN512SiFive7VL
|
|
# ISNE-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# NISB: Resources:
|
|
# NISB-NEXT: [0] - VLEN512SiFive7FDiv
|
|
# NISB-NEXT: [1] - VLEN512SiFive7IDiv
|
|
# NISB-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# NISB-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# NISB-NEXT: [4] - VLEN512SiFive7VA1
|
|
# NISB-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# NISB-NEXT: [6] - VLEN512SiFive7VL
|
|
# NISB-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# NISBE: Resources:
|
|
# NISBE-NEXT: [0] - VLEN512SiFive7FDiv
|
|
# NISBE-NEXT: [1] - VLEN512SiFive7IDiv
|
|
# NISBE-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# NISBE-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# NISBE-NEXT: [4] - VLEN512SiFive7VA1
|
|
# NISBE-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# NISBE-NEXT: [6] - VLEN512SiFive7VL
|
|
# NISBE-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# NISE: Resources:
|
|
# NISE-NEXT: [0] - VLEN512SiFive7FDiv
|
|
# NISE-NEXT: [1] - VLEN512SiFive7IDiv
|
|
# NISE-NEXT: [2] - VLEN512SiFive7PipeA
|
|
# NISE-NEXT: [3] - VLEN512SiFive7PipeB
|
|
# NISE-NEXT: [4] - VLEN512SiFive7VA1
|
|
# NISE-NEXT: [5] - VLEN512SiFive7VCQ
|
|
# NISE-NEXT: [6] - VLEN512SiFive7VL
|
|
# NISE-NEXT: [7] - VLEN512SiFive7VS
|
|
|
|
# ISN: Resource pressure per iteration:
|
|
# ISN-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# ISN-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# ISF: Resource pressure per iteration:
|
|
# ISF-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# ISF-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# ISFB: Resource pressure per iteration:
|
|
# ISFB-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# ISFB-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# ISFBE: Resource pressure per iteration:
|
|
# ISFBE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# ISFBE-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# ISFE: Resource pressure per iteration:
|
|
# ISFE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# ISFE-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# ISNB: Resource pressure per iteration:
|
|
# ISNB-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# ISNB-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# ISNBE: Resource pressure per iteration:
|
|
# ISNBE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# ISNBE-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# ISNE: Resource pressure per iteration:
|
|
# ISNE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# ISNE-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# NISB: Resource pressure per iteration:
|
|
# NISB-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# NISB-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# NISBE: Resource pressure per iteration:
|
|
# NISBE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# NISBE-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# NISE: Resource pressure per iteration:
|
|
# NISE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
|
# NISE-NEXT: - - 1.00 - - 1.00 3.00 -
|
|
|
|
# ALL: Resource pressure by instruction:
|
|
# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
|
|
# ALL-NEXT: - - 1.00 - - - - - vsetvli a3, a2, e16, m1, tu, mu
|
|
# ALL-NEXT: - - - - - 1.00 3.00 - vlm.v v4, (a1)
|