derek.holloway
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95 lines
7.5 KiB
Plaintext
95 lines
7.5 KiB
Plaintext
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p550 -iterations=1 -instruction-tables=full %p/../Inputs/zbb.s | FileCheck %s
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP500Div:1
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# CHECK-NEXT: [1] - SiFiveP500FEXQ0:1
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# CHECK-NEXT: [2] - SiFiveP500FEXQ1:1
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# CHECK-NEXT: [3] - SiFiveP500FloatArith:2 SiFiveP500FEXQ0, SiFiveP500FEXQ1
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# CHECK-NEXT: [4] - SiFiveP500FloatDiv:1
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# CHECK-NEXT: [5] - SiFiveP500IEXQ0:1
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# CHECK-NEXT: [6] - SiFiveP500IEXQ1:1
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# CHECK-NEXT: [7] - SiFiveP500IEXQ2:1
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# CHECK-NEXT: [8] - SiFiveP500IntArith:3 SiFiveP500IEXQ0, SiFiveP500IEXQ1, SiFiveP500IEXQ2
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# CHECK-NEXT: [9] - SiFiveP500Load:1
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# CHECK-NEXT: [10] - SiFiveP500Store:1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith ANDN andn a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith ORN orn a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith XNOR xnor a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith CLZ clz a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith CLZW clzw a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith CTZ ctz a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith CTZW ctzw a0, a0
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# CHECK-NEXT: 1 3 1.00 3 SiFiveP500IEXQ2,SiFiveP500IntArith CPOP cpop a0, a0
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# CHECK-NEXT: 1 3 1.00 3 SiFiveP500IEXQ2,SiFiveP500IntArith CPOPW cpopw a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith MIN min a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith MINU minu a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith MAX max a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith MAXU maxu a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith SEXT_B sext.b a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith SEXT_H sext.h a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith ZEXT_H_RV64 zext.h a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith ROL rol a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith ROLW rolw a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith ROR ror a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith RORW rorw a0, a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith RORI rori a0, a0, 1
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith RORIW roriw a0, a0, 1
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith ORC_B orc.b a0, a0
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# CHECK-NEXT: 1 1 0.33 1 SiFiveP500IntArith REV8_RV64 rev8 a0, a0
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP500Div
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# CHECK-NEXT: [1] - SiFiveP500FEXQ0
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# CHECK-NEXT: [2] - SiFiveP500FEXQ1
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# CHECK-NEXT: [3] - SiFiveP500FloatDiv
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# CHECK-NEXT: [4] - SiFiveP500IEXQ0
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# CHECK-NEXT: [5] - SiFiveP500IEXQ1
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# CHECK-NEXT: [6] - SiFiveP500IEXQ2
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# CHECK-NEXT: [7] - SiFiveP500Load
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# CHECK-NEXT: [8] - SiFiveP500Store
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
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# CHECK-NEXT: - - - - 7.33 7.33 9.33 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - andn a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - orn a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - xnor a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - clz a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - clzw a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - ctz a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - ctzw a0, a0
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# CHECK-NEXT: - - - - - - 1.00 - - cpop a0, a0
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# CHECK-NEXT: - - - - - - 1.00 - - cpopw a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - min a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - minu a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - max a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - maxu a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - sext.b a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - sext.h a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - zext.h a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - rol a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - rolw a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - ror a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - rorw a0, a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - rori a0, a0, 1
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - roriw a0, a0, 1
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - orc.b a0, a0
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# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - rev8 a0, a0
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