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78 lines
5.0 KiB
Plaintext
78 lines
5.0 KiB
Plaintext
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/zbs.s | FileCheck %s
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
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# CHECK-NEXT: [1] - SiFiveP600Div:1
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# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
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# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
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# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
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# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
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# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
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# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
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# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
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# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
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# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
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# CHECK-NEXT: [11] - SiFiveP600LDST:2
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# CHECK-NEXT: [12] - SiFiveP600VDiv:1
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# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
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# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
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# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
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# CHECK-NEXT: [16] - SiFiveP600VLD:1
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# CHECK-NEXT: [17] - SiFiveP600VST:1
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# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BCLR bclr a0, a1, a2
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BCLRI bclri a0, a1, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BEXT bext a0, a1, a2
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BEXTI bexti a0, a1, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BINV binv a0, a1, a2
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BINVI binvi a0, a1, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BSET bset a0, a1, a2
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BSETI bseti a0, a1, 1
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP600Div
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# CHECK-NEXT: [1] - SiFiveP600FEXQ0
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# CHECK-NEXT: [2] - SiFiveP600FEXQ1
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# CHECK-NEXT: [3] - SiFiveP600FloatDiv
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# CHECK-NEXT: [4] - SiFiveP600IEXQ0
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# CHECK-NEXT: [5] - SiFiveP600IEXQ1
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# CHECK-NEXT: [6] - SiFiveP600IEXQ2
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# CHECK-NEXT: [7] - SiFiveP600IEXQ3
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# CHECK-NEXT: [8.0] - SiFiveP600LDST
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# CHECK-NEXT: [8.1] - SiFiveP600LDST
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# CHECK-NEXT: [9] - SiFiveP600VDiv
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# CHECK-NEXT: [10] - SiFiveP600VEXQ0
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# CHECK-NEXT: [11] - SiFiveP600VEXQ1
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# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
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# CHECK-NEXT: [13] - SiFiveP600VLD
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# CHECK-NEXT: [14] - SiFiveP600VST
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
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# CHECK-NEXT: - - - - 2.00 2.00 2.00 2.00 - - - - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bclr a0, a1, a2
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bclri a0, a1, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bext a0, a1, a2
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bexti a0, a1, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - binv a0, a1, a2
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - binvi a0, a1, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bset a0, a1, a2
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bseti a0, a1, 1
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