derek.holloway
7502bf64a4
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182 lines
20 KiB
Plaintext
182 lines
20 KiB
Plaintext
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
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# CHECK-NEXT: [1] - SiFiveP800Div:1
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# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
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# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
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# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
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# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
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# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
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# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
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# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
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# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
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# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
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# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
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# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
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# CHECK-NEXT: [13] - SiFiveP800LD:1
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# CHECK-NEXT: [14] - SiFiveP800LDST:2
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# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
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# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
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# CHECK-NEXT: [17] - SiFiveP800VDiv:1
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# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
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# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
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# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
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# CHECK-NEXT: [21] - SiFiveP800VLD:1
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# CHECK-NEXT: [22] - SiFiveP800VST:1
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# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_ADDI addi a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_ADDIW addiw a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SLTI slti a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SLTIU seqz a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_ANDI andi a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith ORI ori a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith XORI xori a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_SLLI slli a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_SRLI srli a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_SRAI srai a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SLLIW slliw a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SRLIW srliw a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SRAIW sraiw a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_LUI lui a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith AUIPC auipc a1, 1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_ADD add a0, a0, a1
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_ADDW addw a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SLT slt a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SLTU sltu a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_AND and a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_OR or a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_XOR xor a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SLL sll a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SRL srl a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SRA sra a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SLLW sllw a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SRLW srlw a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith SRAW sraw a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_SUB sub a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_SUBW subw a0, a0, a0
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# CHECK-NEXT: 1 1 0.50 1 SiFiveP800Branch JAL jal a0, .Ltmp0
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# CHECK-NEXT: 1 1 0.50 1 SiFiveP800Branch C_JALR jalr a0
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# CHECK-NEXT: 1 1 0.50 1 SiFiveP800Branch BEQ beq a0, a0, .Ltmp1
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# CHECK-NEXT: 1 1 0.50 1 SiFiveP800Branch BNE bne a0, a0, .Ltmp2
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# CHECK-NEXT: 1 1 0.50 1 SiFiveP800Branch BLT blt a0, a0, .Ltmp3
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# CHECK-NEXT: 1 1 0.50 1 SiFiveP800Branch BLTU bltu a0, a0, .Ltmp4
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# CHECK-NEXT: 1 1 0.50 1 SiFiveP800Branch BGE bge a0, a0, .Ltmp5
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# CHECK-NEXT: 1 1 0.50 1 SiFiveP800Branch BGEU bgeu a0, a0, .Ltmp6
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# CHECK-NEXT: 1 1 0.25 1 SiFiveP800IntArith C_ADD add a0, a0, a0
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# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LB lb t0, 0(a0)
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# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LBU lbu t0, 0(a0)
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# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LH lh t0, 0(a0)
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# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LHU lhu t0, 0(a0)
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# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LW lw t0, 0(a0)
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# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LWU lwu t0, 0(a0)
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# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LD ld t0, 0(a0)
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# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP800LDST,SiFiveP800Load SB sb t0, 0(a0)
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# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP800LDST,SiFiveP800Load SH sh t0, 0(a0)
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# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP800LDST,SiFiveP800Load SW sw t0, 0(a0)
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# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP800LDST,SiFiveP800Load SD sd t0, 0(a0)
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# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul CSRRW csrrw t0, 4095, t1
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# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul CSRRS csrrs s3, fflags, s5
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# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul CSRRC csrrc sp, 0, ra
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# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul CSRRWI csrrwi a5, 0, 0
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# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul CSRRSI csrrsi t2, 4095, 31
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# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul CSRRCI csrrci t1, sscratch, 5
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP800Div
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# CHECK-NEXT: [1] - SiFiveP800FEXQ0
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# CHECK-NEXT: [2] - SiFiveP800FEXQ1
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# CHECK-NEXT: [3] - SiFiveP800FloatDiv
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# CHECK-NEXT: [4] - SiFiveP800IEXQ0
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# CHECK-NEXT: [5] - SiFiveP800IEXQ1
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# CHECK-NEXT: [6] - SiFiveP800IEXQ2
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# CHECK-NEXT: [7] - SiFiveP800IEXQ3
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# CHECK-NEXT: [8] - SiFiveP800IEXQ4
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# CHECK-NEXT: [9] - SiFiveP800IEXQ5
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# CHECK-NEXT: [10] - SiFiveP800LD
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# CHECK-NEXT: [11.0] - SiFiveP800LDST
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# CHECK-NEXT: [11.1] - SiFiveP800LDST
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# CHECK-NEXT: [12] - SiFiveP800VDiv
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# CHECK-NEXT: [13] - SiFiveP800VEXQ0
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# CHECK-NEXT: [14] - SiFiveP800VEXQ1
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# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
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# CHECK-NEXT: [16] - SiFiveP800VLD
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# CHECK-NEXT: [17] - SiFiveP800VST
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
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# CHECK-NEXT: - - - - 7.75 13.75 7.75 7.75 4.00 4.00 2.33 4.33 4.33 - - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - addi a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - addiw a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - slti a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - seqz a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andi a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - ori a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - xori a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - slli a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - srli a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - srai a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - slliw a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - srliw a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - sraiw a0, a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - lui a0, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - auipc a1, 1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - add a0, a0, a1
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - addw a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - slt a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - sltu a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - and a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - or a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - xor a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - sll a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - srl a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - sra a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - sllw a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - srlw a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - sraw a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - sub a0, a0, a0
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - subw a0, a0, a0
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# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - jal a0, .Ltmp0
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# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - jalr a0
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# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - beq a0, a0, .Ltmp1
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# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - bne a0, a0, .Ltmp2
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# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - blt a0, a0, .Ltmp3
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# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - bltu a0, a0, .Ltmp4
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# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - bge a0, a0, .Ltmp5
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# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - bgeu a0, a0, .Ltmp6
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# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - add a0, a0, a0
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# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - lb t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - lbu t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - lh t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - lhu t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - lw t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - lwu t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - ld t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - - - - sb t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - - - - sh t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - - - - sw t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - - - - sd t0, 0(a0)
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - csrrw t0, 4095, t1
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - csrrs s3, fflags, s5
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - csrrc sp, 0, ra
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - csrrwi a5, 0, 0
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - csrrsi t2, 4095, 31
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - csrrci t1, sscratch, 5
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