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70 lines
5.0 KiB
Plaintext
70 lines
5.0 KiB
Plaintext
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x180 -iterations=1 -instruction-tables=full %p/../Inputs/mul-div.s | FileCheck %s
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN128X100SiFive7FDiv:1
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# CHECK-NEXT: [1] - VLEN128X100SiFive7IDiv:1
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# CHECK-NEXT: [2] - VLEN128X100SiFive7PipeA:1
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# CHECK-NEXT: [3] - VLEN128X100SiFive7PipeAB:2 VLEN128X100SiFive7PipeA, VLEN128X100SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN128X100SiFive7PipeB:1
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# CHECK-NEXT: [5] - VLEN128X100SiFive7VA1:1
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# CHECK-NEXT: [6] - VLEN128X100SiFive7VCQ:1
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# CHECK-NEXT: [7] - VLEN128X100SiFive7VL:1
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# CHECK-NEXT: [8] - VLEN128X100SiFive7VS:1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 3 1.00 3 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB C_MUL mul a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 3 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB MULH mulh a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 3 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB MULHU mulhu a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 3 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB MULHSU mulhsu a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 3 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB MULW mulw a0, a0, a0
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# CHECK-NEXT: 1 66 65.00 66 VLEN128X100SiFive7IDiv[65],VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB DIV div a0, a1, a2
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# CHECK-NEXT: 1 66 65.00 66 VLEN128X100SiFive7IDiv[65],VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB DIVU divu a0, a1, a2
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# CHECK-NEXT: 1 66 65.00 66 VLEN128X100SiFive7IDiv[65],VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB REM rem a0, a1, a2
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# CHECK-NEXT: 1 66 65.00 66 VLEN128X100SiFive7IDiv[65],VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB REMU remu a0, a1, a2
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# CHECK-NEXT: 1 34 33.00 34 VLEN128X100SiFive7IDiv[33],VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB DIVW divw a0, a1, a2
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# CHECK-NEXT: 1 34 33.00 34 VLEN128X100SiFive7IDiv[33],VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB DIVUW divuw a0, a1, a2
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# CHECK-NEXT: 1 34 33.00 34 VLEN128X100SiFive7IDiv[33],VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB REMW remw a0, a1, a2
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# CHECK-NEXT: 1 34 33.00 34 VLEN128X100SiFive7IDiv[33],VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB REMUW remuw a0, a1, a2
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN128X100SiFive7FDiv
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# CHECK-NEXT: [1] - VLEN128X100SiFive7IDiv
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# CHECK-NEXT: [2] - VLEN128X100SiFive7PipeA
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# CHECK-NEXT: [3] - VLEN128X100SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN128X100SiFive7VA1
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# CHECK-NEXT: [5] - VLEN128X100SiFive7VCQ
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# CHECK-NEXT: [6] - VLEN128X100SiFive7VL
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# CHECK-NEXT: [7] - VLEN128X100SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - 392.00 - 13.00 - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - - 1.00 - - - - mul a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - mulh a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - mulhu a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - mulhsu a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - mulw a0, a0, a0
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# CHECK-NEXT: - 65.00 - 1.00 - - - - div a0, a1, a2
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# CHECK-NEXT: - 65.00 - 1.00 - - - - divu a0, a1, a2
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# CHECK-NEXT: - 65.00 - 1.00 - - - - rem a0, a1, a2
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# CHECK-NEXT: - 65.00 - 1.00 - - - - remu a0, a1, a2
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# CHECK-NEXT: - 33.00 - 1.00 - - - - divw a0, a1, a2
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# CHECK-NEXT: - 33.00 - 1.00 - - - - divuw a0, a1, a2
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# CHECK-NEXT: - 33.00 - 1.00 - - - - remw a0, a1, a2
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# CHECK-NEXT: - 33.00 - 1.00 - - - - remuw a0, a1, a2
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