derek.holloway
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92 lines
7.3 KiB
Plaintext
92 lines
7.3 KiB
Plaintext
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x180 -iterations=1 -instruction-tables=full %p/../Inputs/zbb.s | FileCheck %s
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN128X100SiFive7FDiv:1
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# CHECK-NEXT: [1] - VLEN128X100SiFive7IDiv:1
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# CHECK-NEXT: [2] - VLEN128X100SiFive7PipeA:1
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# CHECK-NEXT: [3] - VLEN128X100SiFive7PipeAB:2 VLEN128X100SiFive7PipeA, VLEN128X100SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN128X100SiFive7PipeB:1
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# CHECK-NEXT: [5] - VLEN128X100SiFive7VA1:1
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# CHECK-NEXT: [6] - VLEN128X100SiFive7VCQ:1
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# CHECK-NEXT: [7] - VLEN128X100SiFive7VL:1
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# CHECK-NEXT: [8] - VLEN128X100SiFive7VS:1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 3 0.50 1 VLEN128X100SiFive7PipeAB ANDN andn a0, a0, a0
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# CHECK-NEXT: 1 3 0.50 1 VLEN128X100SiFive7PipeAB ORN orn a0, a0, a0
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# CHECK-NEXT: 1 3 0.50 1 VLEN128X100SiFive7PipeAB XNOR xnor a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CLZ clz a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CLZW clzw a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CTZ ctz a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CTZW ctzw a0, a0
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# CHECK-NEXT: 1 3 1.00 3 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CPOP cpop a0, a0
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# CHECK-NEXT: 1 3 1.00 3 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CPOPW cpopw a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB MIN min a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB MINU minu a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB MAX max a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB MAXU maxu a0, a0, a0
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# CHECK-NEXT: 1 3 0.50 1 VLEN128X100SiFive7PipeAB C_SEXT_B sext.b a0, a0
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# CHECK-NEXT: 1 3 0.50 1 VLEN128X100SiFive7PipeAB C_SEXT_H sext.h a0, a0
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# CHECK-NEXT: 1 3 0.50 1 VLEN128X100SiFive7PipeAB C_ZEXT_H zext.h a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB ROL rol a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB ROLW rolw a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB ROR ror a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB RORW rorw a0, a0, a0
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB RORI rori a0, a0, 1
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB RORIW roriw a0, a0, 1
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# CHECK-NEXT: 1 3 1.00 1 VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB ORC_B orc.b a0, a0
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# CHECK-NEXT: 1 3 0.50 1 VLEN128X100SiFive7PipeAB REV8_RV64 rev8 a0, a0
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN128X100SiFive7FDiv
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# CHECK-NEXT: [1] - VLEN128X100SiFive7IDiv
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# CHECK-NEXT: [2] - VLEN128X100SiFive7PipeA
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# CHECK-NEXT: [3] - VLEN128X100SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN128X100SiFive7VA1
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# CHECK-NEXT: [5] - VLEN128X100SiFive7VCQ
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# CHECK-NEXT: [6] - VLEN128X100SiFive7VL
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# CHECK-NEXT: [7] - VLEN128X100SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 3.50 20.50 - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 0.50 0.50 - - - - andn a0, a0, a0
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# CHECK-NEXT: - - 0.50 0.50 - - - - orn a0, a0, a0
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# CHECK-NEXT: - - 0.50 0.50 - - - - xnor a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - clz a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - clzw a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - ctz a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - ctzw a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - cpop a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - cpopw a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - min a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - minu a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - max a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - maxu a0, a0, a0
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# CHECK-NEXT: - - 0.50 0.50 - - - - sext.b a0, a0
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# CHECK-NEXT: - - 0.50 0.50 - - - - sext.h a0, a0
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# CHECK-NEXT: - - 0.50 0.50 - - - - zext.h a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - rol a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - rolw a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - ror a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - rorw a0, a0, a0
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# CHECK-NEXT: - - - 1.00 - - - - rori a0, a0, 1
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# CHECK-NEXT: - - - 1.00 - - - - roriw a0, a0, 1
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# CHECK-NEXT: - - - 1.00 - - - - orc.b a0, a0
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# CHECK-NEXT: - - 0.50 0.50 - - - - rev8 a0, a0
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