derek.holloway
7502bf64a4
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56 lines
2.4 KiB
ArmAsm
56 lines
2.4 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
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# TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW)
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# pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV
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# SPEC.
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vsetvli zero, zero, e32, mf2, tu, mu
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vdiv.vv v12, v12, v12
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vsetvli zero, zero, e8, mf8, tu, mu
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vdiv.vv v12, v12, v12
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 4
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# CHECK-NEXT: Total Cycles: 85
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# CHECK-NEXT: Total uOps: 4
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.05
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# CHECK-NEXT: IPC: 0.05
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# CHECK-NEXT: Block RThroughput: 82.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
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# CHECK-NEXT: 1 64 64.00 vdiv.vv v12, v12, v12
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
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# CHECK-NEXT: 1 16 16.00 vdiv.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
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# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
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# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
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# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN512SiFive7VA
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# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
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# CHECK-NEXT: [6] - VLEN512SiFive7VL
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# CHECK-NEXT: [7] - VLEN512SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 2.00 - 82.00 2.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
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# CHECK-NEXT: - - - - 65.00 1.00 - - vdiv.vv v12, v12, v12
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
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# CHECK-NEXT: - - - - 17.00 1.00 - - vdiv.vv v12, v12, v12
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