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161 lines
17 KiB
Plaintext
161 lines
17 KiB
Plaintext
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SMTX100_BQ:2
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# CHECK-NEXT: [1] - SMTX100_FQ:4 SMTX100_FQ0, SMTX100_FQ0, SMTX100_FQ1, SMTX100_FQ1
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# CHECK-NEXT: [2] - SMTX100_FQ0:2
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# CHECK-NEXT: [3] - SMTX100_FQ1:2
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# CHECK-NEXT: [4] - SMTX100_IQ:4 SMTX100_IQ0, SMTX100_IQ0, SMTX100_IQ1, SMTX100_IQ1
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# CHECK-NEXT: [5] - SMTX100_IQ0:2
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# CHECK-NEXT: [6] - SMTX100_IQ1:2
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# CHECK-NEXT: [7] - SMTX100_LSQ:4
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_ADDI addi a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_ADDIW addiw a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SLTI slti a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SLTIU seqz a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_ANDI andi a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ ORI ori a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ XORI xori a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_SLLI slli a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_SRLI srli a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_SRAI srai a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SLLIW slliw a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SRLIW srliw a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SRAIW sraiw a0, a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_LUI lui a0, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ AUIPC auipc a1, 1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_ADD add a0, a0, a1
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_ADDW addw a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SLT slt a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SLTU sltu a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_AND and a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_OR or a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_XOR xor a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SLL sll a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SRL srl a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SRA sra a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SLLW sllw a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SRLW srlw a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ SRAW sraw a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_SUB sub a0, a0, a0
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_SUBW subw a0, a0, a0
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# CHECK-NEXT: 1 2 0.50 2 SMTX100_BQ JAL jal a0, .Ltmp0
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# CHECK-NEXT: 1 2 0.50 2 SMTX100_BQ C_JALR jalr a0
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# CHECK-NEXT: 1 2 0.50 2 SMTX100_BQ BEQ beq a0, a0, .Ltmp1
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# CHECK-NEXT: 1 2 0.50 2 SMTX100_BQ BNE bne a0, a0, .Ltmp2
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# CHECK-NEXT: 1 2 0.50 2 SMTX100_BQ BLT blt a0, a0, .Ltmp3
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# CHECK-NEXT: 1 2 0.50 2 SMTX100_BQ BLTU bltu a0, a0, .Ltmp4
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# CHECK-NEXT: 1 2 0.50 2 SMTX100_BQ BGE bge a0, a0, .Ltmp5
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# CHECK-NEXT: 1 2 0.50 2 SMTX100_BQ BGEU bgeu a0, a0, .Ltmp6
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# CHECK-NEXT: 1 1 0.25 1 SMTX100_IQ C_ADD add a0, a0, a0
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# CHECK-NEXT: 1 3 0.25 * 3 SMTX100_LSQ LB lb t0, 0(a0)
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# CHECK-NEXT: 1 3 0.25 * 3 SMTX100_LSQ LBU lbu t0, 0(a0)
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# CHECK-NEXT: 1 3 0.25 * 3 SMTX100_LSQ LH lh t0, 0(a0)
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# CHECK-NEXT: 1 3 0.25 * 3 SMTX100_LSQ LHU lhu t0, 0(a0)
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# CHECK-NEXT: 1 3 0.25 * 3 SMTX100_LSQ LW lw t0, 0(a0)
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# CHECK-NEXT: 1 3 0.25 * 3 SMTX100_LSQ LWU lwu t0, 0(a0)
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# CHECK-NEXT: 1 3 0.25 * 3 SMTX100_LSQ LD ld t0, 0(a0)
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# CHECK-NEXT: 1 1 0.25 * 1 SMTX100_LSQ SB sb t0, 0(a0)
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# CHECK-NEXT: 1 1 0.25 * 1 SMTX100_LSQ SH sh t0, 0(a0)
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# CHECK-NEXT: 1 1 0.25 * 1 SMTX100_LSQ SW sw t0, 0(a0)
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# CHECK-NEXT: 1 1 0.25 * 1 SMTX100_LSQ SD sd t0, 0(a0)
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# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 CSRRW csrrw t0, 4095, t1
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# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 CSRRS csrrs s3, fflags, s5
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# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 CSRRC csrrc sp, 0, ra
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# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 CSRRWI csrrwi a5, 0, 0
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# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 CSRRSI csrrsi t2, 4095, 31
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# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 CSRRCI csrrci t1, sscratch, 5
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# CHECK: Resources:
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# CHECK-NEXT: [0.0] - SMTX100_BQ
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# CHECK-NEXT: [0.1] - SMTX100_BQ
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# CHECK-NEXT: [1.0] - SMTX100_FQ0
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# CHECK-NEXT: [1.1] - SMTX100_FQ0
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# CHECK-NEXT: [2.0] - SMTX100_FQ1
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# CHECK-NEXT: [2.1] - SMTX100_FQ1
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# CHECK-NEXT: [3.0] - SMTX100_IQ0
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# CHECK-NEXT: [3.1] - SMTX100_IQ0
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# CHECK-NEXT: [4.0] - SMTX100_IQ1
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# CHECK-NEXT: [4.1] - SMTX100_IQ1
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# CHECK-NEXT: [5.0] - SMTX100_LSQ
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# CHECK-NEXT: [5.1] - SMTX100_LSQ
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# CHECK-NEXT: [5.2] - SMTX100_LSQ
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# CHECK-NEXT: [5.3] - SMTX100_LSQ
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3]
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# CHECK-NEXT: 4.00 4.00 - - - - 10.75 10.75 7.75 7.75 2.75 2.75 2.75 2.75
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] Instructions:
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - addi a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - addiw a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - slti a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - seqz a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - andi a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - ori a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - xori a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - slli a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srli a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srai a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - slliw a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srliw a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sraiw a0, a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - lui a0, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - auipc a1, 1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - add a0, a0, a1
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - addw a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - slt a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sltu a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - and a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - or a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - xor a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sll a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srl a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sra a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sllw a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srlw a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sraw a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sub a0, a0, a0
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - subw a0, a0, a0
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - jal a0, .Ltmp0
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - jalr a0
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - beq a0, a0, .Ltmp1
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bne a0, a0, .Ltmp2
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - blt a0, a0, .Ltmp3
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bltu a0, a0, .Ltmp4
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bge a0, a0, .Ltmp5
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bgeu a0, a0, .Ltmp6
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# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - add a0, a0, a0
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lb t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lbu t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lh t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lhu t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lw t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lwu t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 ld t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sb t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sh t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sw t0, 0(a0)
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# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sd t0, 0(a0)
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# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrw t0, 4095, t1
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# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrs s3, fflags, s5
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# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrc sp, 0, ra
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# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrwi a5, 0, 0
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# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrsi t2, 4095, 31
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# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrci t1, sscratch, 5
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