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TheRock/compiler/amd-llvm/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/mul-div.test
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../Inputs/mul-div.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMTX100_BQ:2
# CHECK-NEXT: [1] - SMTX100_FQ:4 SMTX100_FQ0, SMTX100_FQ0, SMTX100_FQ1, SMTX100_FQ1
# CHECK-NEXT: [2] - SMTX100_FQ0:2
# CHECK-NEXT: [3] - SMTX100_FQ1:2
# CHECK-NEXT: [4] - SMTX100_IQ:4 SMTX100_IQ0, SMTX100_IQ0, SMTX100_IQ1, SMTX100_IQ1
# CHECK-NEXT: [5] - SMTX100_IQ0:2
# CHECK-NEXT: [6] - SMTX100_IQ1:2
# CHECK-NEXT: [7] - SMTX100_LSQ:4
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK-NEXT: [7]: Bypass Latency
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
# CHECK-NEXT: [9]: LLVM Opcode Name
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 3 0.50 3 SMTX100_IQ,SMTX100_IQ1 C_MUL mul a0, a0, a0
# CHECK-NEXT: 1 3 0.50 3 SMTX100_IQ,SMTX100_IQ1 MULH mulh a0, a0, a0
# CHECK-NEXT: 1 3 0.50 3 SMTX100_IQ,SMTX100_IQ1 MULHU mulhu a0, a0, a0
# CHECK-NEXT: 1 3 0.50 3 SMTX100_IQ,SMTX100_IQ1 MULHSU mulhsu a0, a0, a0
# CHECK-NEXT: 1 2 0.50 2 SMTX100_IQ,SMTX100_IQ1 MULW mulw a0, a0, a0
# CHECK-NEXT: 1 22 11.00 22 SMTX100_IQ[22],SMTX100_IQ0[22] DIV div a0, a1, a2
# CHECK-NEXT: 1 22 11.00 22 SMTX100_IQ[22],SMTX100_IQ0[22] DIVU divu a0, a1, a2
# CHECK-NEXT: 1 22 11.00 22 SMTX100_IQ[22],SMTX100_IQ0[22] REM rem a0, a1, a2
# CHECK-NEXT: 1 22 11.00 22 SMTX100_IQ[22],SMTX100_IQ0[22] REMU remu a0, a1, a2
# CHECK-NEXT: 1 14 7.00 14 SMTX100_IQ[14],SMTX100_IQ0[14] DIVW divw a0, a1, a2
# CHECK-NEXT: 1 14 7.00 14 SMTX100_IQ[14],SMTX100_IQ0[14] DIVUW divuw a0, a1, a2
# CHECK-NEXT: 1 14 7.00 14 SMTX100_IQ[14],SMTX100_IQ0[14] REMW remw a0, a1, a2
# CHECK-NEXT: 1 14 7.00 14 SMTX100_IQ[14],SMTX100_IQ0[14] REMUW remuw a0, a1, a2
# CHECK: Resources:
# CHECK-NEXT: [0.0] - SMTX100_BQ
# CHECK-NEXT: [0.1] - SMTX100_BQ
# CHECK-NEXT: [1.0] - SMTX100_FQ0
# CHECK-NEXT: [1.1] - SMTX100_FQ0
# CHECK-NEXT: [2.0] - SMTX100_FQ1
# CHECK-NEXT: [2.1] - SMTX100_FQ1
# CHECK-NEXT: [3.0] - SMTX100_IQ0
# CHECK-NEXT: [3.1] - SMTX100_IQ0
# CHECK-NEXT: [4.0] - SMTX100_IQ1
# CHECK-NEXT: [4.1] - SMTX100_IQ1
# CHECK-NEXT: [5.0] - SMTX100_LSQ
# CHECK-NEXT: [5.1] - SMTX100_LSQ
# CHECK-NEXT: [5.2] - SMTX100_LSQ
# CHECK-NEXT: [5.3] - SMTX100_LSQ
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3]
# CHECK-NEXT: - - - - - - 72.00 72.00 2.50 2.50 - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] Instructions:
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mul a0, a0, a0
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mulh a0, a0, a0
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mulhu a0, a0, a0
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mulhsu a0, a0, a0
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mulw a0, a0, a0
# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - div a0, a1, a2
# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - divu a0, a1, a2
# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - rem a0, a1, a2
# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - remu a0, a1, a2
# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - divw a0, a1, a2
# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - divuw a0, a1, a2
# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - remw a0, a1, a2
# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - remuw a0, a1, a2