Files
TheRock/compiler/amd-llvm/llvm/test/tools/llvm-objdump/DXContainer/input-output-signatures.yaml
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

168 lines
6.6 KiB
YAML

# RUN: yaml2obj %s -o %t
# RUN: llvm-objdump -p %t | FileCheck %s --match-full-lines --strict-whitespace
## This test covers llvm-objdump printing private headers for the ISG1, OSG1,
## and PSG1 "parts" of the DX container file format. The test uses a few
## absurdly large values and long string names to ensure that the columns in the
## printed table widen correctly.
--- !dxcontainer
Header:
Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
Version:
Major: 1
Minor: 0
FileSize: 630
PartCount: 3
PartOffsets: [ 64, 124, 184 ]
Parts:
- Name: ISG1
Size: 52
Signature:
Parameters:
- Stream: 0
Name: AAA_HSFoo
Index: 4391238 # This value forces the index column to widen
SystemValue: Undefined
CompType: Float32
Register: 0
Mask: 7
ExclusiveMask: 2
MinPrecision: Default
- Name: OSG1
Size: 52
Signature:
Parameters:
- Stream: 0
Name: SV_Position
Index: 0
SystemValue: Position
CompType: Float32
Register: 2147483647 # This value forces the register column to widen
Mask: 15
ExclusiveMask: 0
MinPrecision: Default
- Name: PSG1
Size: 402
Signature:
Parameters:
- Stream: 0
Name: SV_TessFactor
Index: 0
SystemValue: FinalQuadEdgeTessfactor # The tessfactor forces the SysVal column to widen
CompType: Float32
Register: 0
Mask: 8
ExclusiveMask: 8
MinPrecision: Default
- Stream: 0
Name: BBB
Index: 0
SystemValue: Undefined
CompType: Float32
Register: 0
Mask: 7
ExclusiveMask: 0
MinPrecision: Default
- Stream: 0
Name: SV_TessFactor
Index: 1
SystemValue: FinalQuadEdgeTessfactor
CompType: Float32
Register: 1
Mask: 8
ExclusiveMask: 8
MinPrecision: Default
- Stream: 0
Name: BBB
Index: 1
SystemValue: Undefined
CompType: Float32
Register: 1
Mask: 7
ExclusiveMask: 0
MinPrecision: Default
- Stream: 0
Name: SV_TessFactor
Index: 2
SystemValue: FinalQuadEdgeTessfactor
CompType: Float32
Register: 2
Mask: 8
ExclusiveMask: 8
MinPrecision: Default
- Stream: 0
Name: BBB
Index: 2
SystemValue: Undefined
CompType: Float32
Register: 2
Mask: 7
ExclusiveMask: 0
MinPrecision: Default
- Stream: 0
Name: SV_TessFactor
Index: 3
SystemValue: FinalQuadEdgeTessfactor
CompType: Float32
Register: 3
Mask: 8
ExclusiveMask: 8
MinPrecision: Default
- Stream: 0
Name: SV_InsideTessFactor
Index: 0
SystemValue: FinalQuadInsideTessfactor
CompType: Float32
Register: 4
Mask: 8
ExclusiveMask: 0
MinPrecision: Default
- Stream: 0
Name: SV_InsideTessFactor
Index: 1
SystemValue: FinalQuadInsideTessfactor
CompType: Float32
Register: 5
Mask: 8
ExclusiveMask: 0
MinPrecision: Default
- Stream: 0
Name: AVeryLongStringThatWillForceWidening # This value forces name column to widen
Index: 0
SystemValue: Undefined
CompType: Float32
Register: 6
Mask: 15
ExclusiveMask: 4
MinPrecision: Default
...
# CHECK:; Input signature:
# CHECK-NEXT:;
# CHECK-NEXT:; Name Index Mask Register SysValue Format Used
# CHECK-NEXT:; ------------------------ ------- ----- -------- ---------- ------- -----
# CHECK-NEXT:; AAA_HSFoo 4391238 xyz 0 Undefined Float32 y
# CHECK:; Output signature:
# CHECK-NEXT:;
# CHECK-NEXT:; Name Index Mask Register SysValue Format Used
# CHECK-NEXT:; ------------------------ ----- ----- ---------- ---------- ------- -----
# CHECK-NEXT:; SV_Position 0 xyzw 2147483647 Position Float32
# CHECK:; Patch Constant signature:
# CHECK-NEXT:;
# CHECK-NEXT:; Name Index Mask Register SysValue Format Used
# CHECK-NEXT:; ------------------------------------ ----- ----- -------- ------------------------- ------- -----
# CHECK-NEXT:; SV_TessFactor 0 w 0 FinalQuadEdgeTessfactor Float32 w
# CHECK-NEXT:; BBB 0 xyz 0 Undefined Float32
# CHECK-NEXT:; SV_TessFactor 1 w 1 FinalQuadEdgeTessfactor Float32 w
# CHECK-NEXT:; BBB 1 xyz 1 Undefined Float32
# CHECK-NEXT:; SV_TessFactor 2 w 2 FinalQuadEdgeTessfactor Float32 w
# CHECK-NEXT:; BBB 2 xyz 2 Undefined Float32
# CHECK-NEXT:; SV_TessFactor 3 w 3 FinalQuadEdgeTessfactor Float32 w
# CHECK-NEXT:; SV_InsideTessFactor 0 w 4 FinalQuadInsideTessfactor Float32
# CHECK-NEXT:; SV_InsideTessFactor 1 w 5 FinalQuadInsideTessfactor Float32
# CHECK-NEXT:; AVeryLongStringThatWillForceWidening 0 xyzw 6 Undefined Float32 z