derek.holloway
7502bf64a4
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46 lines
1.5 KiB
ArmAsm
46 lines
1.5 KiB
ArmAsm
@RUN: llvm-mc -triple arm-none-eabi -mcpu=cortex-m33 -filetype=obj %s | llvm-objdump -d --mcpu=cortex-m3 - | FileCheck %s
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@ Check that instructions that are disassembled as <undefined> within an IT
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@ block advance the IT state. This prevents the IT state spilling over into
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@ the next instruction.
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@ The vldmiaeq instruction is disassembled as <undefined> with
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@ -mcpu=cortex-m3 as this does not have a fpu.
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.text
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.fpu fp-armv8
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.thumb
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ite eq
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vldmiaeq r0!, {s16-s31}
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addne r0, r0, r0
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add r1, r1, r1
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itet eq
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vldmiaeq r0!, {s16-s31}
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vldmiane r0!, {s16-s31}
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vldmiaeq r0!, {s16-s31}
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add r0, r0, r0
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add r1, r1, r1
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add r2, r2, r2
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it eq
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vldmiaeq r0!, {s16-s31}
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it ne
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addne r0, r0, r0
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@ CHECK: 0: bf0c ite eq
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@ CHECK-NEXT: 2: ecb0 8a10 <unknown>
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@ CHECK-NEXT: 6: 1800 addne r0, r0, r0
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@ CHECK-NEXT: 8: 4409 add r1, r1
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@ CHECK-NEXT: a: bf0a itet eq
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@ CHECK-NEXT: c: ecb0 8a10 <unknown>
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@ CHECK-NEXT: 10: ecb0 8a10 <unknown>
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@ CHECK-NEXT: 14: ecb0 8a10 <unknown>
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@ CHECK-NEXT: 18: 4400 add r0, r0
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@ CHECK-NEXT: 1a: 4409 add r1, r1
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@ CHECK-NEXT: 1c: 4412 add r2, r2
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@ CHECK-NEXT: 1e: bf08 it eq
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@ CHECK-NEXT: 20: ecb0 8a10 <unknown>
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@ CHECK-NEXT: 24: bf18 it ne
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@ CHECK-NEXT: 26: 1800 addne r0, r0, r0
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