derek.holloway
7502bf64a4
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48 lines
1.7 KiB
ArmAsm
48 lines
1.7 KiB
ArmAsm
## Test that llvm-objdump uses ISA mapping symbols ("$x<ISAString>") to
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## configure per-region disassembly. Covers:
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## - Initial non-V region: V-encoded bytes appear as <unknown>
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## - V-enabled region: same bytes correctly decode as vadd.vv
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## - Restored non-V region (after .option pop): back to <unknown>
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## - Second V region: verifies ISA target cache is reused correctly
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## - rv32 and rv64 both exercise parseNormalizedArchString
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# RUN: llvm-mc -triple=riscv64 -mattr=+c -filetype=obj %s -o %t.64.o
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# RUN: llvm-objdump -d --no-show-raw-insn %t.64.o | FileCheck %s
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#
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# RUN: llvm-mc -triple=riscv32 -mattr=+c -filetype=obj %s -o %t.32.o
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# RUN: llvm-objdump -d --no-show-raw-insn %t.32.o | FileCheck %s
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.text
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# Before any .option arch change the active ISA is rv64gc / rv32gc.
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# A regular instruction decodes normally; a V-encoded word is <unknown>.
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nop
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# CHECK: 0: nop
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.insn 4, 0x02110057 # vadd.vv v0, v1, v2
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# CHECK-NEXT: 2: <unknown>
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## Region 1: V extension enabled via .option arch, +v.
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## The assembler emits "$x<ISA+V>" before vadd.vv; objdump must decode it
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## with the V decoder active.
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.option push
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.option arch, +v
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vadd.vv v0, v1, v2
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# CHECK-NEXT: 6: vadd.vv v0, v1, v2
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.option pop
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## Restored to rv64gc / rv32gc after pop: same encoding is <unknown> again.
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.insn 4, 0x02110057 # vadd.vv v0, v1, v2
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# CHECK-NEXT: a: <unknown>
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## Region 2: enter V again. This exercises the ISATargetCache reuse path
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## (the DisassemblerTarget for ISA+V was already created in Region 1).
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.option push
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.option arch, +v
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vadd.vv v8, v9, v10
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# CHECK-NEXT: e: vadd.vv v8, v9, v10
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.option pop
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## Back to base ISA once more: V encoding is <unknown>.
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.insn 4, 0x02110057 # vadd.vv v0, v1, v2
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# CHECK-NEXT: 12: <unknown>
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