derek.holloway
7502bf64a4
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34 lines
1.2 KiB
ArmAsm
34 lines
1.2 KiB
ArmAsm
## Verify that ISA mapping symbols emitted on .option rvc/.option norvc let
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## llvm-objdump switch the compressed-instruction decoder on and off per
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## region. Starting from a base rv64i / rv32i STI (no C), the middle region
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## is the only one where a compressed encoding should decode; outside the
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## RVC window the 4-byte decoder is in effect.
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# RUN: llvm-mc -triple=riscv64 -filetype=obj %s -o %t.64.o
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# RUN: llvm-objdump -d -M no-aliases --no-show-raw-insn %t.64.o \
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# RUN: | FileCheck %s
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# RUN: llvm-mc -triple=riscv32 -filetype=obj %s -o %t.32.o
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# RUN: llvm-objdump -d -M no-aliases --no-show-raw-insn %t.32.o \
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# RUN: | FileCheck %s
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.text
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## Base (no C): 4-byte nop.
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nop
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# CHECK: 0: addi zero, zero, 0x0
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## Region 1: C enabled. Both an explicit c.nop and a plain nop (which the
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## assembler will relax to c.nop here) decode as compressed, so the per-
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## region decoder clearly has C.
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.option rvc
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c.nop
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# CHECK-NEXT: 4: c.nop
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nop
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# CHECK-NEXT: 6: c.nop
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## Region 2: C disabled again; 4-byte nop round-trips as the full 32-bit
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## encoding, confirming the mapping symbol switched the decoder back.
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.option norvc
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nop
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# CHECK-NEXT: 8: addi zero, zero, 0x0
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