derek.holloway
7502bf64a4
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90 lines
4.9 KiB
MLIR
90 lines
4.9 KiB
MLIR
// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
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// f16 + f16 -> f16
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llvm.func @fadd_f16_f16(%a : f16, %b : f16) -> f16 {
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// CHECK-LABEL: define half @fadd_f16_f16(half %0, half %1) {
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// CHECK-NEXT: %3 = fadd half %0, %1
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// CHECK-NEXT: %4 = fadd half %3, %3
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// CHECK-NEXT: %5 = call half @llvm.nvvm.add.rn.sat.f16(half %4, half %4)
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// CHECK-NEXT: %6 = call half @llvm.nvvm.add.rn.ftz.sat.f16(half %5, half %5)
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// CHECK-NEXT: ret half %6
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// CHECK-NEXT: }
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%f1 = nvvm.addf %a, %b : f16
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%f2 = nvvm.addf %f1, %f1 {rnd = #nvvm.fp_rnd_mode<rn>} : f16
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%f3 = nvvm.addf %f2, %f2 {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<sat>} : f16
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%f4 = nvvm.addf %f3, %f3 {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<sat>, ftz=true} : f16
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llvm.return %f4 : f16
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}
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// bf16 + bf16 -> bf16
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llvm.func @fadd_bf16_bf16(%a : bf16, %b : bf16) -> bf16 {
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// CHECK-LABEL: define bfloat @fadd_bf16_bf16(bfloat %0, bfloat %1) {
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// CHECK-NEXT: %3 = fadd bfloat %0, %1
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// CHECK-NEXT: %4 = fadd bfloat %3, %3
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// CHECK-NEXT: ret bfloat %4
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// CHECK-NEXT: }
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%f1 = nvvm.addf %a, %b : bf16
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%f2 = nvvm.addf %f1, %f1 {rnd = #nvvm.fp_rnd_mode<rn>} : bf16
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llvm.return %f2 : bf16
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}
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// f32 + f32 -> f32
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llvm.func @fadd_f32_f32(%a : f32, %b : f32) -> f32 {
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// CHECK-LABEL: define float @fadd_f32_f32(float %0, float %1) {
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// CHECK-NEXT: %3 = call float @llvm.nvvm.add.rn.f(float %0, float %1)
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// CHECK-NEXT: %4 = call float @llvm.nvvm.add.rn.f(float %3, float %3)
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// CHECK-NEXT: %5 = call float @llvm.nvvm.add.rn.sat.f(float %4, float %4)
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// CHECK-NEXT: %6 = call float @llvm.nvvm.add.rn.ftz.f(float %5, float %5)
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// CHECK-NEXT: %7 = call float @llvm.nvvm.add.rn.ftz.sat.f(float %6, float %6)
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// CHECK-NEXT: %8 = call float @llvm.nvvm.add.rm.f(float %7, float %7)
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// CHECK-NEXT: %9 = call float @llvm.nvvm.add.rm.sat.f(float %8, float %8)
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// CHECK-NEXT: %10 = call float @llvm.nvvm.add.rm.ftz.f(float %9, float %9)
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// CHECK-NEXT: %11 = call float @llvm.nvvm.add.rm.ftz.sat.f(float %10, float %10)
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// CHECK-NEXT: %12 = call float @llvm.nvvm.add.rp.f(float %11, float %11)
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// CHECK-NEXT: %13 = call float @llvm.nvvm.add.rp.sat.f(float %12, float %12)
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// CHECK-NEXT: %14 = call float @llvm.nvvm.add.rp.ftz.f(float %13, float %13)
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// CHECK-NEXT: %15 = call float @llvm.nvvm.add.rp.ftz.sat.f(float %14, float %14)
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// CHECK-NEXT: %16 = call float @llvm.nvvm.add.rz.f(float %15, float %15)
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// CHECK-NEXT: %17 = call float @llvm.nvvm.add.rz.sat.f(float %16, float %16)
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// CHECK-NEXT: %18 = call float @llvm.nvvm.add.rz.ftz.f(float %17, float %17)
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// CHECK-NEXT: %19 = call float @llvm.nvvm.add.rz.ftz.sat.f(float %18, float %18)
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// CHECK-NEXT: ret float %19
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// CHECK-NEXT: }
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%f1 = nvvm.addf %a, %b : f32
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%f2 = nvvm.addf %f1, %f1 {rnd = #nvvm.fp_rnd_mode<rn>} : f32
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%f3 = nvvm.addf %f2, %f2 {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<sat>} : f32
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%f4 = nvvm.addf %f3, %f3 {rnd = #nvvm.fp_rnd_mode<rn>, ftz=true} : f32
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%f5 = nvvm.addf %f4, %f4 {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<sat>, ftz=true} : f32
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%f6 = nvvm.addf %f5, %f5 {rnd = #nvvm.fp_rnd_mode<rm>} : f32
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%f7 = nvvm.addf %f6, %f6 {rnd = #nvvm.fp_rnd_mode<rm>, sat = #nvvm.sat_mode<sat>} : f32
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%f8 = nvvm.addf %f7, %f7 {rnd = #nvvm.fp_rnd_mode<rm>, ftz=true} : f32
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%f9 = nvvm.addf %f8, %f8 {rnd = #nvvm.fp_rnd_mode<rm>, sat = #nvvm.sat_mode<sat>, ftz=true} : f32
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%f10 = nvvm.addf %f9, %f9 {rnd = #nvvm.fp_rnd_mode<rp>} : f32
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%f11 = nvvm.addf %f10, %f10 {rnd = #nvvm.fp_rnd_mode<rp>, sat = #nvvm.sat_mode<sat>} : f32
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%f12 = nvvm.addf %f11, %f11 {rnd = #nvvm.fp_rnd_mode<rp>, ftz=true} : f32
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%f13 = nvvm.addf %f12, %f12 {rnd = #nvvm.fp_rnd_mode<rp>, sat = #nvvm.sat_mode<sat>, ftz=true} : f32
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%f14 = nvvm.addf %f13, %f13 {rnd = #nvvm.fp_rnd_mode<rz>} : f32
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%f15 = nvvm.addf %f14, %f14 {rnd = #nvvm.fp_rnd_mode<rz>, sat = #nvvm.sat_mode<sat>} : f32
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%f16 = nvvm.addf %f15, %f15 {rnd = #nvvm.fp_rnd_mode<rz>, ftz=true} : f32
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%f17 = nvvm.addf %f16, %f16 {rnd = #nvvm.fp_rnd_mode<rz>, sat = #nvvm.sat_mode<sat>, ftz=true} : f32
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llvm.return %f17 : f32
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}
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// f64 + f64 -> f64
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llvm.func @fadd_f64_f64(%a : f64, %b : f64) -> f64 {
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// CHECK-LABEL: define double @fadd_f64_f64(double %0, double %1) {
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// CHECK-NEXT: %3 = call double @llvm.nvvm.add.rn.d(double %0, double %1)
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// CHECK-NEXT: %4 = call double @llvm.nvvm.add.rn.d(double %3, double %3)
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// CHECK-NEXT: %5 = call double @llvm.nvvm.add.rm.d(double %4, double %4)
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// CHECK-NEXT: %6 = call double @llvm.nvvm.add.rp.d(double %5, double %5)
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// CHECK-NEXT: %7 = call double @llvm.nvvm.add.rz.d(double %6, double %6)
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// CHECK-NEXT: ret double %7
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// CHECK-NEXT: }
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%f1 = nvvm.addf %a, %b : f64
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%f2 = nvvm.addf %f1, %f1 {rnd = #nvvm.fp_rnd_mode<rn>} : f64
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%f3 = nvvm.addf %f2, %f2 {rnd = #nvvm.fp_rnd_mode<rm>} : f64
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%f4 = nvvm.addf %f3, %f3 {rnd = #nvvm.fp_rnd_mode<rp>} : f64
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%f5 = nvvm.addf %f4, %f4 {rnd = #nvvm.fp_rnd_mode<rz>} : f64
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llvm.return %f5 : f64
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}
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