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168 lines
3.2 KiB
Plaintext
168 lines
3.2 KiB
Plaintext
# Intel(r) Wireless MMX(tm) technology testcase for WSLL
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# mach: xscale
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# as: -mcpu=xscale+iwmmxt
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.include "testutils.inc"
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start
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.global wsll
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wsll:
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# Enable access to CoProcessors 0 & 1 before
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# we attempt these instructions.
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mvi_h_gr r1, 3
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mcr p15, 0, r1, cr15, cr1, 0
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# Test Halfword Logical Shift Left
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111104
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsllh wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111104
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23406780
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test_h_gr r5, 0xabc0ef00
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# Test Halfword Aritc Shift Left by CG register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111104
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mvi_h_gr r3, 0
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mvi_h_gr r4, 0
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tmcrr wr0, r0, r1
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tmcr wcgr1, r2
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tmcrr wr1, r3, r4
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wsllhg wr1, wr0, wcgr1
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tmrrc r0, r1, wr0
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tmrc r2, wcgr1
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tmrrc r3, r4, wr1
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111104
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test_h_gr r3, 0x23406780
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test_h_gr r4, 0xabc0ef00
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# Test Word Logical Shift Left
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111104
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsllw wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111104
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456780
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test_h_gr r5, 0xabcdef00
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# Test Word Logical Shift Left by CG register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111104
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mvi_h_gr r3, 0
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mvi_h_gr r4, 0
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tmcrr wr0, r0, r1
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tmcr wcgr2, r2
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tmcrr wr1, r3, r4
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wsllwg wr1, wr0, wcgr2
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tmrrc r0, r1, wr0
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tmrc r2, wcgr2
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tmrrc r3, r4, wr1
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111104
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test_h_gr r3, 0x23456780
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test_h_gr r4, 0xabcdef00
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# Test Double Word Logical Shift Left
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdefc
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mvi_h_gr r2, 0x11111104
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wslld wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdefc
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test_h_gr r2, 0x11111104
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456780
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test_h_gr r5, 0xabcdefc1
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# Test Double Word Logical Shift Left by CG register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdefc
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mvi_h_gr r2, 0x11111104
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mvi_h_gr r3, 0
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mvi_h_gr r4, 0
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tmcrr wr0, r0, r1
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tmcr wcgr3, r2
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tmcrr wr1, r3, r4
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wslldg wr1, wr0, wcgr3
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tmrrc r0, r1, wr0
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tmrc r2, wcgr3
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tmrrc r3, r4, wr1
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdefc
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test_h_gr r2, 0x11111104
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test_h_gr r3, 0x23456780
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test_h_gr r4, 0xabcdefc1
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pass
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