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252 lines
4.9 KiB
Plaintext
252 lines
4.9 KiB
Plaintext
# Intel(r) Wireless MMX(tm) technology testcase for WSUB
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# mach: xscale
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# as: -mcpu=xscale+iwmmxt
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.include "testutils.inc"
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start
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.global wsub
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wsub:
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# Enable access to CoProcessors 0 & 1 before
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# we attempt these instructions.
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mvi_h_gr r1, 3
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mcr p15, 0, r1, cr15, cr1, 0
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# Test Unsaturated Byte subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubb wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abcdef
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# Test Unsigned saturated Byte subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubbus wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abcd00
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# Test Signed saturated Byte subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubbss wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abcdef
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# Test Unsaturated Halfword subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubh wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abccef
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# Test Unsigned saturated Halfword subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubhus wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abccef
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# Test Signed saturated Halfword subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubhss wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abccef
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# Test Unsaturated Word subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubw wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abccef
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# Test Unsigned saturated Word subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubwus wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abccef
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# Test Signed saturated Word subtraction
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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wsubwss wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x01234567
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test_h_gr r5, 0x89abccef
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pass
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