derek.holloway
7502bf64a4
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234 lines
3.7 KiB
ArmAsm
234 lines
3.7 KiB
ArmAsm
# Hitachi H8 testcase 'ldm', 'stm'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.data
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.align 4
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_stack: .long 0,1,2,3,4,5,6,7,8,9,0,0,0,0,0,0
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.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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_stack_top:
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start
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.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
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stm_2reg:
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set_grs_a5a5
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mov #_stack_top, er7
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mov #2, er2
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mov #3, er3
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set_ccr_zero
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stm er2-er3, @-sp
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test_cc_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_h_gr32 2 er2
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test_h_gr32 3 er3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_h_gr32 _stack_top-8, er7
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mov @_stack_top-4, er0
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cmp #2, er0
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bne fail1
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mov @_stack_top-8, er0
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cmp #3, er0
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bne fail1
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mov @_stack_top-12, er0
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cmp #0, er0
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bne fail1
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stm_3reg:
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set_grs_a5a5
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mov #_stack_top, er7
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mov #4, er4
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mov #5, er5
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mov #6, er6
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set_ccr_zero
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stm er4-er6, @-sp
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test_cc_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_h_gr32 4 er4
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test_h_gr32 5 er5
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test_h_gr32 6 er6
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test_h_gr32 _stack_top-12, er7
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mov @_stack_top-4, er0
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cmp #4, er0
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bne fail1
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mov @_stack_top-8, er0
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cmp #5, er0
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bne fail1
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mov @_stack_top-12, er0
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cmp #6, er0
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bne fail1
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mov @_stack_top-16, er0
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cmp #0, er0
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bne fail1
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stm_4reg:
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set_grs_a5a5
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mov #_stack_top, er7
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mov #1, er0
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mov #2, er1
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mov #3, er2
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mov #4, er3
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set_ccr_zero
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stm er0-er3, @-sp
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test_cc_clear
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test_h_gr32 1 er0
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test_h_gr32 2 er1
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test_h_gr32 3 er2
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test_h_gr32 4 er3
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test_gr_a5a5 4 ; Make sure other general regs not disturbed
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_h_gr32 _stack_top-16, er7
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mov @_stack_top-4, er0
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cmp #1, er0
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bne fail1
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mov @_stack_top-8, er0
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cmp #2, er0
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bne fail1
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mov @_stack_top-12, er0
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cmp #3, er0
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bne fail1
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mov @_stack_top-16, er0
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cmp #4, er0
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bne fail1
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mov @_stack_top-20, er0
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cmp #0, er0
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bne fail1
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ldm_2reg:
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set_grs_a5a5
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mov #_stack, er7
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set_ccr_zero
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ldm @sp+, er2-er3
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test_cc_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_h_gr32 1 er2
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test_h_gr32 0 er3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_h_gr32 _stack+8, er7
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ldm_3reg:
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set_grs_a5a5
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mov #_stack+4, er7
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set_ccr_zero
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ldm @sp+, er4-er6
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test_cc_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_h_gr32 3 er4
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test_h_gr32 2 er5
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test_h_gr32 1 er6
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test_h_gr32 _stack+16, er7
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ldm_4reg:
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set_grs_a5a5
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mov #_stack+4, er7
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set_ccr_zero
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ldm @sp+, er0-er3
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test_cc_clear
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test_h_gr32 4 er0
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test_h_gr32 3 er1
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test_h_gr32 2 er2
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test_h_gr32 1 er3
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test_gr_a5a5 4 ; Make sure other general regs not disturbed
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_h_gr32 _stack+20, er7
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.endif
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pushpop:
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set_grs_a5a5
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.if (sim_cpu == h8300)
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mov #_stack_top, r7
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mov #12, r1
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mov #34, r2
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mov #56, r3
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push r1
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push r2
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push r3
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pop r4
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pop r5
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pop r6
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test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed
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test_h_gr16 12 r1
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test_h_gr16 34 r2
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test_h_gr16 56 r3
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test_h_gr16 56 r4
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test_h_gr16 34 r5
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test_h_gr16 12 r6
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mov #_stack_top, r0
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cmp.w r0, r7
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bne fail1
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.else
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mov #_stack_top, er7
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mov #12, er1
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mov #34, er2
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mov #56, er3
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push er1
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push er2
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push er3
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pop er4
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pop er5
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pop er6
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test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed
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test_h_gr32 12 er1
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test_h_gr32 34 er2
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test_h_gr32 56 er3
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test_h_gr32 56 er4
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test_h_gr32 34 er5
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test_h_gr32 12 er6
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test_h_gr32 _stack_top, er7
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.endif
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pass
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exit 0
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fail1: fail
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