TheRock/rocm-libraries/projects/hipblaslt/tensilelite/Tensile/Components/MAC_F64.py

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from rocisa.code import Module
from rocisa.container import vgpr
from rocisa.enum import DataTypeEnum
from rocisa.instruction import VFmaF64, SSetPrior
from ..Common.DataType import DataType
from ..Component import MAC

class FMA_F64_Plain(MAC):
    """
    Plain MAC instruction implementation
    """
    asmCaps = {"v_fma_f64": True}
    kernel = {"ProblemType": {"MacDataTypeA": DataType(DataTypeEnum.Double),
                              "MacDataTypeB": DataType(DataTypeEnum.Double)}}

    def __call__(self, writer, tPA, tPB, m, innerUnroll):
        kernel = writer.states.kernel

        module = Module("MAC_F64_Plain")
        module.addComment(self.commentHeader())

        vars = {}
        vars["m"] = m
        vars["ThreadTile0"] = kernel["ThreadTile0"]

        for b in range(0, kernel["ThreadTile1"]):
            vars["b"] = b
            for a in range(0, kernel["ThreadTile0"]):
                vars["a"] = a
                for iui in range(0, innerUnroll):
                    vars["iui"] = iui

                    cStr = "ValuC+%d" % ((vars["a"]+vars["b"]*vars["ThreadTile0"])*2)
                    aStr = "ValuA_X%d_I%d+%d" % (vars["m"], vars["iui"], vars["a"]*2)
                    bStr = "ValuB_X%d_I%d+%d" % (vars["m"], vars["iui"], vars["b"]*2)

                    module.add(VFmaF64(dst=vgpr(cStr, 2), src0=vgpr(aStr, 2),
                                       src1=vgpr(bStr, 2), src2=vgpr(cStr, 2)))
                    if (b == 0) and (a == 0) and (iui == 0):
                        module.add(SSetPrior(prior=1, comment="Raise priority while processing macs"))

        module.add(SSetPrior(prior=0, comment="Reset priority after macs"))

        return module