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269 lines
9.7 KiB
Python
269 lines
9.7 KiB
Python
################################################################################
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#
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# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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# SPDX-License-Identifier: MIT
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################################################################################
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from typing import Any, Optional
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from rocisa.instruction import SWaitCnt
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from Tensile.Components.CMSValidator import verify_scc_overlap
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from cms_validation_base import CMSValidationTestBase
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class TestValidateSCCOverlap(CMSValidationTestBase):
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needs_timeline = False
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def validation_function(self, sched, kernel_dict, codePathIdx, timeline=None):
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return verify_scc_overlap(sched, kernel_dict, codePathIdx)
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def setup_method(self, method=None, *, kernel_updates: Optional[dict[str, Any]] = None):
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kernel_updates = kernel_updates.copy() if kernel_updates else {}
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kernel_updates.update({"MIWaveTileA": 4, "MIWaveTileB": 4, "DirectToLds": 1})
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super().setup_method(method, kernel_updates=kernel_updates)
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def test_gr_simple(self):
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self.kernel["Use64bShadowLimit"] = 1
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assert self.num_vmfma == 32
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optSchedule = {
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"SYNC": [0],
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"GRIncA": [[0, 0, 1, 1, 2, 2, 3, 3, 4]],
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"GRIncB": [[5, 5, 6, 6, 7, 7, 8, 8, 9]],
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"GRA": [[10, 11]],
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"GRB": [[12, 13]],
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'LWSA': [[31]],
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'LWSB': [[31]]
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}
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syncCode = [
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SWaitCnt(dscnt=-1, vlcnt=-1, vscnt=-1, comment=""),
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]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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# GRA in GRIncA
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optSchedule["GRA"] = [[2, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRA at index 2 can't be between GRIncA 2-3 due to SCC usage.")
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# GRB in GRIncB
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optSchedule["GRA"] = [[10, 11]]
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optSchedule["GRB"] = [[6, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRB at index 6 can't be between GRIncB 6-7 due to SCC usage.")
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def test_gr_declaration_order(self):
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self.kernel["Use64bShadowLimit"] = 1
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assert self.num_vmfma == 32
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optSchedule = {
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"SYNC": [0],
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"GRA": [[16, 17]],
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"GRIncA": [[0, 0, 1,
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2, 3,
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4, 5,
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6, 7]],
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"GRIncB": [[8, 8, 9,
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10, 11,
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12, 13,
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14, 15]],
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"GRB": [[18, 19]],
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'LWSA': [[31]],
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'LWSB': [[31]]
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}
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syncCode = [
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SWaitCnt(dscnt=-1, vlcnt=-1, vscnt=-1, comment=""),
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]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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# GRA just before GRIncA
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optSchedule["GRA"] = [[0, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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# GRB just before GRIncB
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optSchedule["GRB"] = [[8, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRB at index 8 can't be between GRIncB 8-9 due to SCC usage.")
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# GRA just after GRIncA
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optSchedule["GRB"] = [[12, 13]]
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optSchedule["GRA"] = [[1, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRA at index 1 can't be between GRIncA 0-1 due to SCC usage.")
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# GRB just after GRIncA
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optSchedule["GRA"] = [[10, 11]]
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optSchedule["GRB"] = [[1, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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def test_gr_interval(self):
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self.kernel["Use64bShadowLimit"] = 1
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assert self.num_vmfma == 32
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optSchedule = {
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"SYNC": [0],
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"GRIncA": [[0, 0, 1,
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2, 3,
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4, 5,
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6, 7]],
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"GRIncB": [[8, 8, 9,
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10, 11,
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12, 13,
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14, 15]],
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"GRA": [[16, 17]],
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"GRB": [[18, 19]],
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'LWSA': [[31]],
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'LWSB': [[31]]
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}
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syncCode = [
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SWaitCnt(dscnt=-1, vlcnt=-1, vscnt=-1, comment=""),
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]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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optSchedule["GRA"] = [[0, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRA at index 0 can't be between GRIncA 0-1 due to SCC usage.")
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optSchedule["GRA"] = [[2, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRA at index 2 can't be between GRIncA 2-3 due to SCC usage.")
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optSchedule["GRA"] = [[3, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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optSchedule["GRB"] = [[6, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRB at index 6 can't be between GRIncA 6-7 due to SCC usage.")
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def test_gr_noshadow(self):
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self.kernel["Use64bShadowLimit"] = 0
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assert self.num_vmfma == 32
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optSchedule = {
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"SYNC": [0],
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"GRIncA": [[0, 0, 1,
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2, 3,
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4]],
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"GRA": [[16, 17]],
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"GRIncB": [[6, 7, 8,
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9, 10,
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10]],
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"GRB": [[18, 19]],
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'LWSA': [[31]],
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'LWSB': [[31]]
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}
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syncCode = [
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SWaitCnt(dscnt=-1, vlcnt=-1, vscnt=-1, comment=""),
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]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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# GRA inside GRInc interval
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optSchedule["GRA"] = [[0, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRA at index 0 can't be between GRIncA 0-1 due to SCC usage.")
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# GRA just after GRInc interval
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optSchedule["GRA"] = [[1, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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# GRB after GRIncB-10
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optSchedule["GRB"] = [[10, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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# GRA before GRIncB-10 -> middle of interval
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optSchedule["GRA"] = [[10, 11]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRA at index 10 can't be between GRIncB 9-10 due to SCC usage.")
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def test_lws(self):
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self.kernel["Use64bShadowLimit"] = 0
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assert self.num_vmfma == 32
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optSchedule = {
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"SYNC": [0],
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'LWSA': [[31]],
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"GRIncA": [[0, 0, 1,
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2, 3,
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4]],
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"GRA": [[16, 17]],
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"GRIncB": [[6, 7, 8,
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9, 10,
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10]],
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"GRB": [[18, 19]],
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'LWSB': [[31]]
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}
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syncCode = [
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SWaitCnt(dscnt=-1, vlcnt=-1, vscnt=-1, comment=""),
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]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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optSchedule["LWSA"] = [[0]]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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optSchedule["LWSA"] = [[1]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"LWSA at index 1 can't be between GRIncA 0-1 due to SCC usage.")
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optSchedule["LWSA"] = [[2]]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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optSchedule["LWSB"] = [[9]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"LWSB at index 9 can't be between GRIncB 9-10 due to SCC usage.")
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def test_gr_inc_together(self):
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self.kernel["Use64bShadowLimit"] = 0
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assert self.num_vmfma == 32
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optSchedule = {
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"SYNC": [0],
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'LWSA': [[31]],
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"GRIncA": [[0, 0, 1,
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3, 4,
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4]],
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"GRA": [[16, 17]],
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"GRIncB": [[6, 7, 8,
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9, 10,
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10]],
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"GRB": [[18, 19]],
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'LWSB': [[31]]
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}
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syncCode = [
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SWaitCnt(dscnt=-1, vlcnt=-1, vscnt=-1, comment=""),
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]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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optSchedule["GRIncB"] = [[0, 0, 1,
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9, 10,
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10]]
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self.validate(optSchedule, syncCode, 1, None, None, 0,
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"GRIncB at index 0 can't be between GRIncA 0-1 due to SCC usage.")
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optSchedule["GRIncB"] = [[1, 1, 2,
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9, 10,
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10]]
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self.validate(optSchedule, syncCode, 1, None, None, 0, None)
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