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117 lines
4.2 KiB
C++
117 lines
4.2 KiB
C++
// Copyright © Advanced Micro Devices, Inc., or its affiliates.
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// SPDX-License-Identifier: MIT
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#pragma once
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#include <gtest/gtest.h>
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#include <algorithm>
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#include <cstdint>
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#include <memory>
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#include <vector>
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#include <hipdnn_data_sdk/utilities/Tensor.hpp>
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namespace hipdnn_ragged_test
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{
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using namespace hipdnn_data_sdk::utilities;
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// Canonical BSHD-packed geometry shared across the ragged-tensor and iterator tests:
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// dims [B, S_max, H, D], strides {S*H*D, H*D, D, 1}. B=2 (batch0 seq=2, batch1 seq=3),
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// seqStride = H*D = 4, off[B] = 20.
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inline const std::vector<int64_t> K_DIMS = {2, 3, 2, 2};
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inline const std::vector<int64_t> K_STRIDES = {12, 4, 2, 1};
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inline const std::vector<int64_t> K_OFFSETS = {0, 8, 20};
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/// Build a rank-4 ragged_offset aux (dims {B+1, 1, 1, 1}) of the given index element
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/// type and populate it with @p offsets (element units).
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template <typename IndexT>
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inline std::shared_ptr<ITensor> makeOffsetAux(const std::vector<int64_t>& offsets)
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{
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const auto count = static_cast<int64_t>(offsets.size());
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auto aux = std::make_shared<Tensor<IndexT>>(std::vector<int64_t>{count, 1, 1, 1});
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for(int64_t i = 0; i < count; ++i)
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{
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aux->setHostValue(static_cast<IndexT>(offsets[static_cast<size_t>(i)]), i, 0, 0, 0);
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}
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return aux;
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}
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/// Per-batch sequence extent for BSHD-packed ragged geometry.
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inline int64_t seqExtent(const std::vector<int64_t>& offsets, int64_t seqStride, int64_t b)
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{
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return (offsets[static_cast<size_t>(b) + 1] - offsets[static_cast<size_t>(b)]) / seqStride;
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}
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/// elementCount/elementSpace/isPacked reporting (RFC 0014 §4.5.6/4.5.7).
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template <typename T>
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inline void checkReporting(const TensorBase<T>& tensor, int64_t total)
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{
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EXPECT_EQ(tensor.elementCount(), static_cast<size_t>(total));
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EXPECT_EQ(tensor.elementSpace(), static_cast<size_t>(total));
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EXPECT_FALSE(tensor.isPacked());
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}
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/// Writes a unique value to every valid logical position and confirms it lands at the
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/// expected physical slot `ragged_offset[b] + s*stride1 + h*stride2 + d*stride3`.
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template <typename T>
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inline void checkAddressing(TensorBase<T>& tensor,
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const std::vector<int64_t>& dims,
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const std::vector<int64_t>& strides,
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const std::vector<int64_t>& offsets)
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{
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const int64_t batchCount = dims[0];
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const int64_t heads = dims[2];
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const int64_t headDim = dims[3];
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const int64_t seqStride = strides[1];
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T counter{1};
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for(int64_t b = 0; b < batchCount; ++b)
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{
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for(int64_t s = 0; s < seqExtent(offsets, seqStride, b); ++s)
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{
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for(int64_t h = 0; h < heads; ++h)
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{
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for(int64_t d = 0; d < headDim; ++d)
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{
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tensor.setHostValue(counter, b, s, h, d);
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const int64_t expectedPhysical
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= offsets[static_cast<size_t>(b)] + s * seqStride + h * strides[2] + d;
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const auto* base = static_cast<const T*>(tensor.memory().hostData());
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EXPECT_EQ(base[expectedPhysical], counter)
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<< "b=" << b << " s=" << s << " h=" << h << " d=" << d;
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++counter;
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}
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}
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}
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}
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}
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/// Iterating begin()..end() visits exactly `ragged_offset[B]` physical elements, each
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/// exactly once. The visited offsets are the union of all per-batch ranges
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/// `[ragged_offset[b], ragged_offset[b+1])`, which partitions `[0, off[B])`. This checks
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/// the visited *set*, not the order.
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template <typename T>
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inline void checkIteration(TensorBase<T>& tensor, const std::vector<int64_t>& offsets)
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{
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const int64_t total = offsets.back();
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const auto* base = static_cast<const T*>(tensor.memory().hostData());
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std::vector<int64_t> visited;
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for(auto it = tensor.begin(); it != tensor.end(); ++it)
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{
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const auto* ptr = static_cast<const T*>(*it);
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visited.push_back(ptr - base);
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}
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ASSERT_EQ(static_cast<int64_t>(visited.size()), total);
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std::sort(visited.begin(), visited.end());
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for(int64_t i = 0; i < total; ++i)
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{
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EXPECT_EQ(visited[static_cast<size_t>(i)], i) << "missing/duplicate physical offset";
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}
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}
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} // namespace hipdnn_ragged_test
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