derek.holloway
7502bf64a4
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248 lines
7.3 KiB
YAML
248 lines
7.3 KiB
YAML
# ########################################################################
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# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights Reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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#
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# ########################################################################
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---
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include: rocsparse_common.yaml
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Definitions:
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- &alpha_beta_range_quick
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- { alpha: 1.0, beta: 1.0, alphai: 1.0, betai: 0.5 }
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- &alpha_beta_range_checkin
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- { alpha: 0.0, beta: 1.5, alphai: 0.0, betai: 0.3 }
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- { alpha: 2.0, beta: 0.0, alphai: 0.5, betai: 0.3 }
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- { alpha: 3.0, beta: 1.7, alphai: -0.5, betai: 0.8 }
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- &alpha_beta_range_nightly
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- { alpha: -0.5, beta: -0.2, alphai: 1.0, betai: 1.9 }
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Tests:
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# C = alpha * A + beta * B
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# Quick
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- name: spgeam_mult_csr
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category: quick
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function: spgeam_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex_real
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M: [300]
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N: [300]
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K: [254]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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baseB: [rocsparse_index_base_zero]
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baseC: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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- name: spgeam_mult_csr_file
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category: quick
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function: spgeam_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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M: 1
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N: [300]
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K: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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baseB: [rocsparse_index_base_zero]
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baseC: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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filename: [nos1,
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nos2,
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nos3,
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nos4,
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nos5,
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nos6,
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nos7]
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- name: spgeam_mult_csr_file
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category: quick
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function: spgeam_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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M: 1
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N: [22, 300]
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K: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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baseB: [rocsparse_index_base_one]
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baseC: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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filename: [mplate]
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# Pre-checkin
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- name: spgeam_csr_bad_arg
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category: pre_checkin
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function: spgeam_csr_bad_arg
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex_real
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- name: spgeam_csr_extra
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category: pre_checkin
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baseA: *all_rocsparse_index_base
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baseB: *all_rocsparse_index_base
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baseC: *all_rocsparse_index_base
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function: spgeam_csr_extra
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- name: spgeam_mult_csr
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category: pre_checkin
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function: spgeam_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex_real
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M: [2000]
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N: [2000]
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K: [1956, 9478]
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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baseB: [rocsparse_index_base_zero]
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baseC: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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- name: spgeam_mult_csr_file
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category: pre_checkin
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function: spgeam_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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M: 1
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N: [2000]
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K: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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baseB: [rocsparse_index_base_one]
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baseC: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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filename: [scircuit]
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- name: spgeam_mult_csr_file
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category: pre_checkin
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function: spgeam_csr
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indextype: *i32
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precision: *single_double_precisions
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M: 1
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N: [1500]
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K: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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baseB: [rocsparse_index_base_one]
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baseC: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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filename: [rma10,
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mac_econ_fwd500]
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- name: spgeam_mult_csr_file
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category: pre_checkin
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function: spgeam_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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M: 1
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N: [1000]
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K: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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baseB: [rocsparse_index_base_zero]
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baseC: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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filename: [mplate]
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# Nightly
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- name: spgeam_mult_csr
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category: nightly
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function: spgeam_csr
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indextype: *i32
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precision: *single_double_precisions_complex_real
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M: [54672, 842323]
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N: [2354, 1492312]
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K: [657, 743434]
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alpha_beta: *alpha_beta_range_nightly
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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baseB: [rocsparse_index_base_zero]
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baseC: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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- name: spgeam_mult_csr_file
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category: nightly
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function: spgeam_csr
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indextype: *i64i32
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precision: *single_double_precisions
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M: 1
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N: [6712, 1492312]
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K: 1
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alpha_beta: *alpha_beta_range_nightly
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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baseB: [rocsparse_index_base_zero]
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baseC: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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filename: [bibd_22_8,
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bmwcra_1,
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amazon0312,
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Chebyshev4,
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sme3Dc,
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webbase-1M,
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shipsec1]
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- name: spgeam_mult_csr_file
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category: nightly
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function: spgeam_csr
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indextype: *i64
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precision: *single_double_precisions_complex
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M: 1
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N: [5690, 901923]
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K: 1
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alpha_beta: *alpha_beta_range_nightly
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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baseB: [rocsparse_index_base_zero]
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baseC: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spgeam_alg: [rocsparse_spgeam_alg_default]
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filename: [Chevron4]
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