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# ########################################################################
# Copyright (C) 2026 Advanced Micro Devices, Inc. All rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.
#
# ########################################################################
---
include: rocsparse_common.yaml
Definitions:
- &M_N_range_quick
- { M: 50, N: 50 }
- { M: 187, N: 187 }
- &M_N_range_checkin
- { M: 0, N: 0 }
- { M: 79, N: 79 }
- { M: 428, N: 428 }
- &M_N_range_nightly
- { M: 9381, N: 9381 }
- { M: 37017, N: 37017 }
- { M: 505194, N: 505194 }
- &M_N_range_extra
- { M: 10, N: 10 }
- { M: 235, N: 235 }
- { M: 1200, N: 1200 }
- &M_N_bsr_range_quick
- { M: 72, N: 72 }
- { M: 360, N: 360 }
- &M_N_bsr_range_checkin
- { M: 0, N: 0 }
- { M: 79, N: 79 }
- { M: 430, N: 430 }
- &M_N_bsr_range_nightly
- { M: 9381, N: 9381 }
- { M: 37017, N: 37017 }
- { M: 505194, N: 505194 }
Tests:
- name: spic0_extra
category: quick
M_N: *M_N_range_extra
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
function: spic0_extra
indextype: *i32i32_i64i32_i64i64
batch_count: [1,2]
- name: spic0
category: quick
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_range_quick
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_zero]
indextype: *i32
batch_count: [1,2]
- name: spic0
category: quick
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_range_quick
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_random]
indextype: *i32
batch_count: [2,3]
- name: spic0
category: quick
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_quick
block_dim: [4]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_zero]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [1,2,4]
- name: spic0
category: quick
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_quick
block_dim: [4]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [8]
- name: spic0_bad_arg
category: pre_checkin
function: spic0_bad_arg
precision: *single_double_precisions_complex_real
formatA: [rocsparse_format_csr, rocsparse_format_bsr]
- name: spic0
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_quick
block_dim: [1, 9]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [1,4]
- name: spic0_file
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex_real
M: 1
N: 1
block_dim: [3]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos5]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex_real
M: 1
N: 1
block_dim: [2, 4, 6]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos5]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex
M: 1
N: 1
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron2]
indextype: *i64
- name: spic0
category: pre_checkin
function: spic0
precision: *double_only_precisions_complex
M_N: *M_N_range_checkin
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_random]
indextype: *i32
batch_count: [1,4]
- name: spic0_file
category: pre_checkin
function: spic0
precision: *double_precision
M: 1
N: 1
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_file_rocalution]
indextype: *i64i32
filename: [rma10,
mc2depi,
nos1,
nos2]
indextype: *i64i32
- name: spic0_extra
category: pre_checkin
function: spic0_extra
- name: spic0_file
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex
M: 1
N: 1
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron3]
indextype: *i32
- name: spic0_graph_test
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_range_quick
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_random]
graph_test: true
indextype: *i32
- name: spic0_file
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex_real
M: 1
N: 1
block_dim: [3, 9]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos7]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [16]
- name: spic0
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_checkin
block_dim: [3, 6, 15, 27]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: pre_checkin
function: spic0
precision: *single_double_precisions
M: 1
N: 1
block_dim: [5, 21]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_row]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos4,
nos6,
nos1,
nos2]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: pre_checkin
function: spic0
precision: *double_precision
M: 1
N: 1
block_dim: [5, 8]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_one]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos3,
nos5,
nos7]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex
M: 1
N: 1
block_dim: [8, 16]
apol: [rocsparse_analysis_policy_force]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_row]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron2]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_graph_test
category: pre_checkin
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_quick
block_dim: [1, 4, 9, 17]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
graph_test: true
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions_complex_real
M: 1
N: 1
block_dim: [27]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos7]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [128]
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions_complex_real
M: 1
N: 1
block_dim: [2, 4, 5, 10]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos4]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [1,2,4]
- name: spic0_file
category: nightly
function: spic0
precision: *double_precision
M: 1
N: 1
block_dim: [5, 8]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_one]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [scircuit]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions_complex_real
M: 1
N: 1
block_dim: [3, 5, 15]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos6]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0
category: nightly
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_range_nightly
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_random]
indextype: *i32
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions
M: 1
N: 1
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_file_rocalution]
filename: [mac_econ_fwd500,
nos4,
nos6,
scircuit]
indextype: *i64
batch_count: [1,2,3]
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions
M: 1
N: 1
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_file_rocalution]
filename: [amazon0312,
nos3,
nos5,
nos7]
indextype: *i32
batch_count: [2]
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions
M: 1
N: 1
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chebyshev4]
skip_hardware: gfx940, gfx941
indextype: *i32
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions_complex
M: 1
N: 1
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron4]
indextype: *i32
- name: spic0_file
category: stress
function: spic0
precision: *single_double_precisions
M: 1
N: 1
transA: [rocsparse_operation_none]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
formatA: [rocsparse_format_csr]
matrix: [rocsparse_matrix_file_rocalution]
filename: [ASIC_320k]
skip_hardware: gfx940, gfx941
indextype: *i32
# Nightly
- name: spic0
category: nightly
function: spic0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_nightly
block_dim: [5, 35]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions
M: 1
N: 1
block_dim: [3]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [amazon0312,
mac_econ_fwd500]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [1,2,4]
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions
M: 1
N: 1
block_dim: [3]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chebyshev4]
skip_hardware: gfx940, gfx941
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spic0_file
category: nightly
function: spic0
precision: *single_double_precisions_complex
M: 1
N: 1
block_dim: [9]
apol: [rocsparse_analysis_policy_force]
baseA: [rocsparse_index_base_one]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron4]
formatA: [rocsparse_format_bsr]
indextype: *i32
# Stress
- name: spic0_file
category: stress
function: spic0
precision: *single_double_precisions
M: 1
N: 1
block_dim: [3]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [ASIC_320k]
skip_hardware: gfx940, gfx941
formatA: [rocsparse_format_bsr]
indextype: *i32
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