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TheRock/rocm-libraries/projects/rocsparse/clients/tests/test_spilu0.yaml
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# ########################################################################
# Copyright (C) 2026 Advanced Micro Devices, Inc. All rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.
#
# ########################################################################
---
include: rocsparse_common.yaml
Definitions:
- &M_N_csr_range_quick
- { M: 50, N: 50 }
- { M: 187, N: 187 }
- &M_N_csr_range_checkin
- { M: 0, N: 0 }
- { M: 79, N: 79 }
- { M: 361, N: 361 }
- &M_N_csr_range_nightly
- { M: 9381, N: 9381 }
- { M: 37017, N: 37017 }
- { M: 505193, N: 505193 }
- &M_N_bsr_range_quick
- { M: 50, N: 50 }
- { M: 187, N: 187 }
- &M_N_bsr_range_checkin
- { M: 0, N: 0 }
- { M: 79, N: 79 }
- { M: 430, N: 430 }
- &M_N_bsr_range_nightly
- { M: 9381, N: 9381 }
- { M: 37017, N: 37017 }
- { M: 505194, N: 505194 }
Tests:
- name: spilu0_bad_arg
category: pre_checkin
function: spilu0_bad_arg
precision: *single_double_precisions_complex_real
formatA: [rocsparse_format_csr]
- name: spilu0
category: quick
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_csr_range_quick
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_zero]
formatA: [rocsparse_format_csr]
indextype: *i32
- name: spilu0
category: quick
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_csr_range_quick
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_csr]
indextype: *i64
batch_count: [1,4]
- name: spilu0
category: pre_checkin
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_csr_range_quick
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_csr]
indextype: *i64
batch_count: [2,8,16]
- name: spilu0
category: quick
function: spilu0
precision: *single_double_precisions
M_N: *M_N_csr_range_quick
numericboost: [1]
boosttol: [0.05]
boostval: [0.2]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_csr]
indextype: *i32
batch_count: [1,2]
- name: spilu0
category: pre_checkin
function: spilu0
precision: *single_double_precisions
M_N: *M_N_csr_range_quick
numericboost: [0, 1]
boosttol: [0.05, 0.5, 0.79, 1.1]
boostval: [0.2, 1.0, 1.5]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_csr]
indextype: *i32
batch_count: [8,16]
- name: spilu0
category: pre_checkin
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_csr_range_checkin
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_csr]
indextype: *i64
- name: spilu0
category: nightly
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_csr_range_nightly
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_csr]
indextype: *i32i32_i64i32_i64i64
- name: spilu0_file
category: quick
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
numericboost: [1]
boosttol: [0.05]
boostval: [1.0]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos4]
formatA: [rocsparse_format_csr]
batch_count: [2]
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
numericboost: [0, 1]
boosttol: [0.05]
boostval: [1.0]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos6,
nos1,
nos2]
formatA: [rocsparse_format_csr]
batch_count: [4]
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
numericboost: [0, 1]
boosttol: [0.05, 0.79]
boostval: [1.0]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
matrix: [rocsparse_matrix_file_rocalution]
filename: [scircuit]
formatA: [rocsparse_format_csr]
batch_count: [2,4]
- name: spilu0_file
category: pre_checkin
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos5,
nos7]
formatA: [rocsparse_format_csr]
indextype: *i64i32
batch_count: [1,3]
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_file_rocalution]
filename: [mc2depi,
nos1,
nos3,
nos5,
nos7]
formatA: [rocsparse_format_csr]
indextype: *i32i32_i64i32_i64i64
batch_count: [1,3]
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_file_rocalution]
filename: [bmwcra_1,
amazon0312,
sme3Dc,
webbase-1M]
formatA: [rocsparse_format_csr]
indextype: *i64
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chebyshev4]
skip_hardware: gfx940, gfx941
formatA: [rocsparse_format_csr]
indextype: *i32i32_i64i32_i64i64
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions_complex
M: 1
N: 1
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron3]
formatA: [rocsparse_format_csr]
indextype: *i32
batch_count: [2]
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions_complex
M: 1
N: 1
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron4]
formatA: [rocsparse_format_csr]
indextype: *i64
- name: spilu0_graph_test
category: pre_checkin
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_csr_range_quick
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_random]
graph_test: true
formatA: [rocsparse_format_csr]
- name: spilu0_extra
category: pre_checkin
function: spilu0_extra
formatA: [rocsparse_format_csr]
- name: spilu0_file
category: stress
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
matrix: [rocsparse_matrix_file_rocalution]
filename: [ASIC_320k]
skip_hardware: gfx940, gfx941
formatA: [rocsparse_format_csr]
- name: spilu0
category: quick
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_quick
block_dim: [4]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_zero]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spilu0
category: quick
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_quick
block_dim: [1, 4]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [4]
- name: spilu0
category: nightly
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_nightly
block_dim: [5]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spilu0_file
category: quick
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
block_dim: [5]
numericboost: [0]
boosttol: [0.01]
boostval: [1.2]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_row]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos1,
nos2]
formatA: [rocsparse_format_bsr]
indextype: *i64
batch_count: [3]
- name: spilu0
category: pre_checkin
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_quick
block_dim: [3]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i64i32
batch_count: [16]
- name: spilu0
category: pre_checkin
function: spilu0
precision: *single_precision
M_N: *M_N_bsr_range_quick
block_dim: [32]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [2,3,4]
- name: spilu0
category: pre_checkin
function: spilu0
precision: *single_double_precisions
M_N: *M_N_bsr_range_quick
block_dim: [9]
numericboost: [0, 1]
boosttol: [0.2, 0.5, 0.9, 1.1]
boostval: [0.5, 1.2]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spilu0
category: nightly
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_checkin
block_dim: [3, 6]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [1,3]
- name: spilu0_file
category: pre_checkin
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
block_dim: [5]
numericboost: [1]
boosttol: [0.01]
boostval: [1.2]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_row]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos1,
nos2]
formatA: [rocsparse_format_bsr]
indextype: *i64
batch_count: [3]
- name: spilu0_file
category: pre_checkin
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
block_dim: [5]
numericboost: [1]
boosttol: [0.01]
boostval: [1.2]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_row]
matrix: [rocsparse_matrix_file_rocalution]
filename: [nos4,
nos6,
nos1,
nos2]
formatA: [rocsparse_format_bsr]
indextype: *i64
batch_count: [2, 4]
- name: spilu0_file
category: pre_checkin
function: spilu0
precision: *double_precision
M: 1
N: 1
block_dim: [5, 8]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_one]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [mc2depi]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spilu0_graph_test
category: pre_checkin
function: spilu0
precision: *single_double_precisions
M_N: *M_N_bsr_range_quick
block_dim: [1, 4, 9]
numericboost: [0, 1]
boosttol: [0.2, 0.5, 0.9, 1.1]
boostval: [0.5, 1.2]
apol: [rocsparse_analysis_policy_reuse]
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
graph_test: true
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spilu0
category: nightly
function: spilu0
precision: *single_double_precisions_complex_real
M_N: *M_N_bsr_range_checkin
block_dim: [15, 27]
apol: *all_rocsparse_analysis_policy
baseA: *all_rocsparse_index_base
direction: *all_rocsparse_direction
matrix: [rocsparse_matrix_random]
formatA: [rocsparse_format_bsr]
indextype: *i32i32_i64i32_i64i64
batch_count: [1,3]
- name: spilu0_file
category: nightly
function: spilu0
precision: *double_precision
M: 1
N: 1
block_dim: [5, 8]
apol: *all_rocsparse_analysis_policy
baseA: [rocsparse_index_base_one]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [scircuit,
mac_econ_fwd500]
formatA: [rocsparse_format_bsr]
indextype: *i32
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions
M: 1
N: 1
block_dim: [3]
apol: [rocsparse_analysis_policy_reuse]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [amazon0312,
nos3,
nos5,
nos7]
formatA: [rocsparse_format_bsr]
indextype: *i64
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions_complex
M: 1
N: 1
block_dim: [7]
apol: [rocsparse_analysis_policy_force]
baseA: [rocsparse_index_base_zero]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron2]
formatA: [rocsparse_format_bsr]
indextype: *i32
batch_count: [2,3]
- name: spilu0_file
category: nightly
function: spilu0
precision: *single_double_precisions_complex
M: 1
N: 1
block_dim: [9]
apol: [rocsparse_analysis_policy_force]
baseA: [rocsparse_index_base_one]
direction: [rocsparse_direction_column]
matrix: [rocsparse_matrix_file_rocalution]
filename: [Chevron4]
formatA: [rocsparse_format_bsr]
indextype: *i32
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