derek.holloway
7502bf64a4
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815 lines
23 KiB
YAML
815 lines
23 KiB
YAML
# ########################################################################
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# Copyright (C) 2022-2026 Advanced Micro Devices, Inc. All rights Reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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#
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# ########################################################################
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---
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include: rocsparse_common.yaml
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Definitions:
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- &alpha_beta_range_quick
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- { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 }
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- &alpha_beta_range_checkin
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- { alpha: 3.0, beta: 1.0, alphai: 2.0, betai: -0.5 }
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- &alpha_beta_range_nightly
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- { alpha: -0.5, beta: 0.5, alphai: 1.0, betai: -0.5 }
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- { alpha: -1.0, beta: -0.5, alphai: 0.0, betai: 0.0 }
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- &alpha_beta_range_stress
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- { alpha: 1.0, beta: 0.0, alphai: 0.0, betai: 0.0 }
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Tests:
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- name: spmm_csc_bad_arg
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category: pre_checkin
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function: spmm_csc_bad_arg
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex_real
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# Default-algorithm auto-selection (CSC). Drives the full buffer_size ->
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# preprocess -> compute pipeline on an extremely column-skewed and an extremely
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# uniform matrix and checks the default result against the analytic product and
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# both explicit load-balanced kernels. The test builds its own matrices, so it
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# ignores the index/precision below.
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- name: spmm_csc_extra
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category: quick
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function: spmm_csc_extra
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indextype: *i32
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precision: *double_only_precisions
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# ##############################
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# # Quick
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# ##############################
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- name: spmm_csc
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category: quick
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function: spmm_csc
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indextype: *i32
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precision: *double_only_precisions
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M: [300]
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N: [223]
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K: [647]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spmm_alg: [rocsparse_spmm_alg_csr]
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orderB: [rocsparse_order_column]
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orderC: [rocsparse_order_row]
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- name: spmm_csc
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category: quick
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function: spmm_csc
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indextype: *i64
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precision: *single_double_precisions_complex_real
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M: [300]
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N: [300]
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K: [223]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spmm_alg: [rocsparse_spmm_alg_csr]
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orderB: [rocsparse_order_column]
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orderC: [rocsparse_order_column]
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- name: spmm_csc_file
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category: quick
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function: spmm_csc
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indextype: *i64i32
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precision: *double_only_precisions
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M: 1
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N: [64]
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K: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr, rocsparse_spmm_alg_csr_row_split]
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orderB: [rocsparse_order_column, rocsparse_order_row]
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orderC: [rocsparse_order_column]
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filename: [nos3,
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nos4]
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- name: spmm_csc_file
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category: quick
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function: spmm_csc
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indextype: *i32
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precision: *single_double_precisions
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M: 1
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N: [256]
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K: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_none, rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr]
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orderB: [rocsparse_order_column, rocsparse_order_row]
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orderC: [rocsparse_order_row]
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filename: [nos1,
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nos4]
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- name: spmm_csc_file
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category: quick
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function: spmm_csc
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indextype: *i64
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precision: *double_only_precisions
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M: 1
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N: [128]
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K: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_none, rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr]
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orderB: [rocsparse_order_column, rocsparse_order_row]
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orderC: [rocsparse_order_row]
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filename: [nos3,
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nos7]
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- name: spmm_csc_file
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category: quick
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function: spmm_csc
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indextype: *i32_i64
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precision: *double_only_precisions
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M: 1
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N: [42]
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K: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_none, rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr, rocsparse_spmm_alg_csr_row_split]
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orderB: [rocsparse_order_column, rocsparse_order_row]
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orderC: [rocsparse_order_column]
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filename: [nos2,
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nos3,
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nos6,
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nos7]
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- name: spmm_csc_file
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category: quick
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function: spmm_csc
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indextype: *i64i32
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precision: *single_double_precisions_complex
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M: 1
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N: [7]
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K: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr]
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orderB: [rocsparse_order_column]
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orderC: [rocsparse_order_row]
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filename: [Chevron2]
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- name: spmm_csc
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category: quick
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function: spmm_csc
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indextype: *i32
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precision: *int8_int8_int32_int32_abct_precision
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M: [300]
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N: [219]
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K: [614]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none, rocsparse_operation_transpose]
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transB: [rocsparse_operation_none, rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spmm_alg: [rocsparse_spmm_alg_csr]
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orderB: [rocsparse_order_row]
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orderC: [rocsparse_order_row]
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rand_gen_min: -128.0
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rand_gen_max: 127.0
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convert_to_int: true
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- name: spmm_csc
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category: quick
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function: spmm_csc
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indextype: *i64
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precision: *int8_int8_float32_float32_abct_precision
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M: [300]
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N: [300]
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K: [278]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none, rocsparse_operation_transpose]
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transB: [rocsparse_operation_none, rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spmm_alg: [rocsparse_spmm_alg_csr_row_split]
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orderB: [rocsparse_order_column]
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orderC: [rocsparse_order_row]
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rand_gen_min: -128.0
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rand_gen_max: 127.0
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convert_to_int: true
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- name: spmm_csc
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category: quick
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function: spmm_csc
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indextype: *i32
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precision: *float16_float16_float32_float32_abct_precision
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M: [300]
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N: [19, 47]
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K: [48364]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spmm_alg: [rocsparse_spmm_alg_csr_row_split]
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orderB: [rocsparse_order_row]
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orderC: [rocsparse_order_row]
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- name: spmm_csc
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category: quick
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function: spmm_csc
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indextype: *i32
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precision: *bfloat16_bfloat16_float32_float32_abct_precision
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M: [300]
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N: [35]
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K: [80000]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spmm_alg: [rocsparse_spmm_alg_csr_row_split]
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orderB: [rocsparse_order_row, rocsparse_order_column]
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orderC: [rocsparse_order_row]
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- name: spmm_csc
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category: quick
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function: spmm_csc
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indextype: *i32
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precision: [*float16_float16_float32_float32_abct_precision, *bfloat16_bfloat16_float32_float32_abct_precision]
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M: [300]
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N: [16, 32]
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K: [512]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none, rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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spmm_alg: [rocsparse_spmm_alg_csr_row_split, rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path]
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orderB: [rocsparse_order_column]
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orderC: [rocsparse_order_column]
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##############################
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# Precheckin
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##############################
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- name: spmm_csc
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category: pre_checkin
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function: spmm_csc
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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M: [311]
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N: [441]
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K: [82]
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_none, rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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spmm_alg: [rocsparse_spmm_alg_csr]
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orderB: [rocsparse_order_row, rocsparse_order_column]
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orderC: [rocsparse_order_column]
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- name: spmm_csc_file
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category: pre_checkin
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function: spmm_csc
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indextype: *i32_i64
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precision: *double_only_precisions_complex
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M: 1
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N: [16]
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K: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr_row_split]
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orderB: [rocsparse_order_row]
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orderC: [rocsparse_order_column]
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filename: [mplate]
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- name: spmm_csc_file
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category: pre_checkin
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function: spmm_csc
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indextype: *i32i32_i64i32_i64i64
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precision: *double_only_precisions
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M: 1
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N: [34]
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K: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr_row_split]
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orderB: [rocsparse_order_column]
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orderC: [rocsparse_order_column]
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filename: [webbase-1M]
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- name: spmm_csc_file
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category: pre_checkin
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function: spmm_csc
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indextype: *i64i32
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precision: *double_only_precisions_complex
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M: 1
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N: [44]
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K: 1
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tolm: 4
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_transpose]
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transB: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr_row_split]
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orderB: [rocsparse_order_row]
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orderC: [rocsparse_order_row]
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filename: [mplate]
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- name: spmm_csc_file
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category: pre_checkin
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function: spmm_csc
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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M: 1
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N: [9]
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K: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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transB: [rocsparse_operation_transpose]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spmm_alg: [rocsparse_spmm_alg_csr]
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orderB: [rocsparse_order_row]
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|
orderC: [rocsparse_order_column]
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|
filename: [amazon0312]
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|
|
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- name: spmm_csc_file
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|
category: pre_checkin
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|
function: spmm_csc
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|
indextype: *i64i32
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|
precision: *double_only_precisions
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|
M: 1
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|
N: [47]
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K: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_transpose]
|
|
transB: [rocsparse_operation_transpose]
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|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr_row_split]
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|
orderB: [rocsparse_order_column]
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|
orderC: [rocsparse_order_row]
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|
filename: [mac_econ_fwd500]
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|
|
|
- name: spmm_csc_file
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|
category: pre_checkin
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|
function: spmm_csc
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|
indextype: *i64i32
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|
precision: *single_double_precisions_complex
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|
M: 1
|
|
N: [4]
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|
K: 1
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|
alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_one]
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|
matrix: [rocsparse_matrix_file_rocalution]
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|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_row]
|
|
orderC: [rocsparse_order_column]
|
|
filename: [Chevron3]
|
|
|
|
- name: spmm_csc_file
|
|
category: pre_checkin
|
|
function: spmm_csc
|
|
indextype: *i32i32_i64i32_i64i64
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [6]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_checkin
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_row]
|
|
orderC: [rocsparse_order_column]
|
|
filename: [scircuit]
|
|
|
|
- name: spmm_csc_file
|
|
category: pre_checkin
|
|
function: spmm_csc
|
|
indextype: *i64i32
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [21]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_checkin
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_column]
|
|
filename: [bibd_22_8]
|
|
|
|
- name: spmm_csc_file
|
|
category: pre_checkin
|
|
function: spmm_csc
|
|
indextype: *i64i32
|
|
precision: *double_only_precisions_complex
|
|
M: 1
|
|
N: [17]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_checkin
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_one]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_row]
|
|
orderC: [rocsparse_order_row]
|
|
filename: [Chebyshev4]
|
|
|
|
- name: spmm_csc_file
|
|
category: pre_checkin
|
|
function: spmm_csc
|
|
indextype: *i32i32_i64i32_i64i64
|
|
precision: *int8_int8_int32_int32_abct_precision
|
|
M: 1
|
|
N: [27]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_quick
|
|
transA: [rocsparse_operation_none, rocsparse_operation_transpose]
|
|
transB: [rocsparse_operation_none, rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr_nnz_split]
|
|
orderB: [rocsparse_order_row]
|
|
orderC: [rocsparse_order_column]
|
|
filename: [nos2,
|
|
nos5]
|
|
rand_gen_min: -128.0
|
|
rand_gen_max: 127.0
|
|
convert_to_int: true
|
|
|
|
- name: spmm_csc
|
|
category: pre_checkin
|
|
function: spmm_csc
|
|
indextype: *i32
|
|
precision: *float16_float16_float32_float32_abct_precision
|
|
M: [2000]
|
|
N: [27, 51]
|
|
K: [29856]
|
|
alpha_beta: *alpha_beta_range_checkin
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_random]
|
|
spmm_alg: [rocsparse_spmm_alg_csr_nnz_split]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_column]
|
|
|
|
- name: spmm_csc
|
|
category: pre_checkin
|
|
function: spmm_csc
|
|
indextype: *i32
|
|
precision: [*float16_float16_float32_float32_abct_precision, *bfloat16_bfloat16_float32_float32_abct_precision]
|
|
M: [1024]
|
|
N: [32, 64]
|
|
K: [1024]
|
|
alpha_beta: *alpha_beta_range_checkin
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none, rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_random]
|
|
spmm_alg: [rocsparse_spmm_alg_csr_row_split, rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_column]
|
|
|
|
- name: spmm_csc_graph_test
|
|
category: pre_checkin
|
|
function: spmm_csc
|
|
indextype: *i32i32_i64i32_i64i64
|
|
precision: *double_only_precisions
|
|
M: [223, 485]
|
|
N: [223]
|
|
K: [223, 485, 647]
|
|
alpha_beta: *alpha_beta_range_quick
|
|
transA: [rocsparse_operation_none, rocsparse_operation_transpose]
|
|
transB: [rocsparse_operation_none, rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_random]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_column]
|
|
graph_test: true
|
|
|
|
|
|
##############################
|
|
# Nightly
|
|
##############################
|
|
|
|
- name: spmm_csc
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i32i32_i64i32_i64i64
|
|
precision: *single_double_precisions_complex_real
|
|
M: [431]
|
|
N: [273]
|
|
K: [97]
|
|
alpha_beta: *alpha_beta_range_nightly
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_random]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_row]
|
|
|
|
- name: spmm_csc_file
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i64i32
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [14]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_nightly
|
|
transA: [rocsparse_operation_transpose]
|
|
transB: [rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_one]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr, rocsparse_spmm_alg_csr_row_split]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_column]
|
|
filename: [sme3Dc]
|
|
|
|
# Fails from rounding. Need to investigate better ways to quantify rounding errors and hoipefully add back later
|
|
# - name: spmm_csc_file
|
|
# category: nightly
|
|
# function: spmm_csc
|
|
# indextype: *i32_i64
|
|
# precision: *double_only_precisions
|
|
# M: 1
|
|
# N: [48]
|
|
# K: 1
|
|
# tolm: 4
|
|
# alpha_beta: *alpha_beta_range_nightly
|
|
# transA: [rocsparse_operation_transpose]
|
|
# transB: [rocsparse_operation_none]
|
|
# baseA: [rocsparse_index_base_one]
|
|
# matrix: [rocsparse_matrix_file_rocalution]
|
|
# spmm_alg: [rocsparse_spmm_alg_csr, rocsparse_spmm_alg_csr_row_split]
|
|
# orderB: [rocsparse_order_row]
|
|
# orderC: [rocsparse_order_row]
|
|
# filename: [shipsec1]
|
|
|
|
- name: spmm_csc_file
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i32_i64
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [48]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_nightly
|
|
transA: [rocsparse_operation_transpose]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_one]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr, rocsparse_spmm_alg_csr_row_split]
|
|
orderB: [rocsparse_order_row]
|
|
orderC: [rocsparse_order_row]
|
|
filename: [webbase-1M]
|
|
|
|
- name: spmm_csc_file
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i32_i64
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [21]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_nightly
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_one]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_row]
|
|
orderC: [rocsparse_order_column]
|
|
filename: [ASIC_320k]
|
|
|
|
- name: spmm_csc_file
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i32_i64
|
|
precision: *single_double_precisions_complex
|
|
M: 1
|
|
N: [12]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_nightly
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_row]
|
|
filename: [Chevron3, Chevron4]
|
|
|
|
- name: spmm_csc_file
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i32_i64
|
|
precision: *single_double_precisions_complex
|
|
M: 1
|
|
N: [5]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_nightly
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_column]
|
|
filename: [Chevron4]
|
|
|
|
- name: spmm_csc_file
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i32_i64
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [52]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_nightly
|
|
transA: [rocsparse_operation_transpose]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_one]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr_row_split]
|
|
orderB: [rocsparse_order_row]
|
|
orderC: [rocsparse_order_row]
|
|
filename: [mc2depi]
|
|
|
|
- name: spmm_csc_file
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i32i32_i64i32_i64i64
|
|
precision: *int8_int8_float32_float32_abct_precision
|
|
M: 1
|
|
N: [91]
|
|
K: 1
|
|
alpha_beta: *alpha_beta_range_quick
|
|
transA: [rocsparse_operation_none, rocsparse_operation_transpose]
|
|
transB: [rocsparse_operation_none, rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr_merge_path]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_column]
|
|
filename: [scircuit]
|
|
rand_gen_min: -128.0
|
|
rand_gen_max: 127.0
|
|
convert_to_int: true
|
|
|
|
- name: spmm_csc
|
|
category: nightly
|
|
function: spmm_csc
|
|
indextype: *i32
|
|
precision: *float16_float16_float32_float32_abct_precision
|
|
M: [5881]
|
|
N: [20, 58]
|
|
K: [31546]
|
|
alpha_beta: *alpha_beta_range_nightly
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_random]
|
|
spmm_alg: [rocsparse_spmm_alg_csr_merge_path]
|
|
orderB: [rocsparse_order_column]
|
|
orderC: [rocsparse_order_row]
|
|
|
|
##############################
|
|
# STRESS
|
|
##############################
|
|
- name: spmm_csc
|
|
category: stress
|
|
hardware: [gfx90a]
|
|
function: spmm_csc
|
|
indextype: *i32
|
|
precision: *single_only_precisions
|
|
M: [30000000]
|
|
N: [2]
|
|
K: [300000000]
|
|
alpha_beta: *alpha_beta_range_stress
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_transpose]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_tridiagonal]
|
|
spmm_alg: [rocsparse_spmm_alg_csr, rocsparse_spmm_alg_csr_row_split]
|
|
orderB: [rocsparse_order_row, rocsparse_order_column]
|
|
orderC: [rocsparse_order_row, rocsparse_order_column]
|
|
|
|
- name: spmm_csc_file
|
|
category: stress
|
|
hardware: [gfx90a]
|
|
function: spmm_csc
|
|
indextype: *i32
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [2]
|
|
K: 1
|
|
ld_multiplier_B: [9354]
|
|
ld_multiplier_C: [7523]
|
|
alpha_beta: *alpha_beta_range_stress
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_row, rocsparse_order_column]
|
|
orderC: [rocsparse_order_row, rocsparse_order_column]
|
|
filename: [sme3Dc]
|
|
|
|
- name: spmm_csc_file
|
|
category: stress
|
|
hardware: [gfx90a]
|
|
function: spmm_csc
|
|
indextype: *i32
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [2]
|
|
K: 1
|
|
ld_multiplier_B: [9354]
|
|
ld_multiplier_C: [7523]
|
|
alpha_beta: *alpha_beta_range_stress
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_row, rocsparse_order_column]
|
|
orderC: [rocsparse_order_row, rocsparse_order_column]
|
|
filename: [bmwcra_1]
|
|
rand_gen_min: -100.0
|
|
rand_gen_max: 100.0
|
|
convert_to_int: true
|
|
|
|
- name: spmm_csc_file
|
|
category: stress
|
|
hardware: [gfx90a]
|
|
function: spmm_csc
|
|
indextype: *i32
|
|
precision: *double_only_precisions
|
|
M: 1
|
|
N: [2]
|
|
K: 1
|
|
ld_multiplier_B: [9354]
|
|
ld_multiplier_C: [7523]
|
|
alpha_beta: *alpha_beta_range_stress
|
|
transA: [rocsparse_operation_none]
|
|
transB: [rocsparse_operation_none]
|
|
baseA: [rocsparse_index_base_zero]
|
|
matrix: [rocsparse_matrix_file_rocalution]
|
|
spmm_alg: [rocsparse_spmm_alg_csr]
|
|
orderB: [rocsparse_order_row]
|
|
orderC: [rocsparse_order_row, rocsparse_order_column]
|
|
filename: [shipsec1]
|