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141 lines
6.2 KiB
C++
141 lines
6.2 KiB
C++
/*******************************************************************************
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*
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* MIT License
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*
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* Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*******************************************************************************/
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#ifndef DLRM_DOT_FWD_HPP
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#define DLRM_DOT_FWD_HPP
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#include <rocwmma/internal/utils.hpp>
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#include "./common.hpp"
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namespace rocwmma
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{
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template <typename DataT, uint TILE_DIM>
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__global__ void __launch_bounds__(128, 1) dlrmDotFwd(const DataT* __restrict input,
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DataT* __restrict output,
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float32_t* acc,
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uint m,
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uint k,
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uint b,
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uint inputBatchOffset,
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uint outputBatchOffset,
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uint accBatchOffset)
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{
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using MappingA = MappingUtil<TILE_DIM, TILE_DIM, DataT, row_major>;
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using MappingB = MappingUtil<TILE_DIM, TILE_DIM, DataT, col_major>;
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using MappingC = MappingUtil<TILE_DIM, TILE_DIM, DataT, row_major>;
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using MappingAcc = MappingUtil<TILE_DIM, TILE_DIM, float32_t, row_major>;
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using FragA = fragment<matrix_a, TILE_DIM, TILE_DIM, TILE_DIM, DataT, row_major>;
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using FragB = fragment<matrix_b, TILE_DIM, TILE_DIM, TILE_DIM, DataT, col_major>;
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using FragAcc = fragment<accumulator, TILE_DIM, TILE_DIM, TILE_DIM, float32_t>;
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// Copy bottom MLP to output
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// Threads with a global index < k are responsible for copying MLP data
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auto globalThreadCoord = blockIdx.x * blockDim.x + threadIdx.x;
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auto count = k / blockDim.x;
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count = (count > 1) ? count : 1;
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if(blockIdx.x == 0 && blockIdx.y == 0)
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{
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for(int i = 0; i < count; i++)
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{
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if(i * blockDim.x + globalThreadCoord < k)
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{
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output[outputBatchOffset * blockIdx.z + i * blockDim.x + globalThreadCoord]
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= input[inputBatchOffset * blockIdx.z + i * blockDim.x + globalThreadCoord];
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}
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}
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}
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// Target output block
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auto matrixCoordC = MappingC::matrixCoord();
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if(get<0>(matrixCoordC) < m && get<1>(matrixCoordC) < m)
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{
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// Initialize accumulator
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auto fragAcc = FragAcc();
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fill_fragment(fragAcc, static_cast<float32_t>(0));
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// Setup starting addresses
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auto* inputWithOffset = input + inputBatchOffset * blockIdx.z;
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auto* addrA
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= MappingA::dataCoord(inputWithOffset, make_coord2d(get<0>(matrixCoordC), 0), k);
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auto* addrB
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= MappingB::dataCoord(inputWithOffset, make_coord2d(0, get<1>(matrixCoordC)), k);
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// Setup address increments.
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// A steps BlockK through m x k
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// B steps BlockK through k x m
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auto incrA = MappingA::dataOffset(make_coord2d(0, TILE_DIM), k);
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auto incrB = MappingB::dataOffset(make_coord2d(TILE_DIM, 0), k);
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auto count = k / TILE_DIM;
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for(int i = 0; i < count; i++)
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{
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auto fragA = FragA();
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auto fragB = FragB();
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// Load and multiply
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load_matrix_sync(fragA, addrA, k);
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load_matrix_sync(fragB, addrB, k);
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mma_sync(fragAcc, fragA, fragB, fragAcc);
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addrA += incrA;
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addrB += incrB;
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}
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// Store fragAcc to global acc
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auto* accWithOffset = acc + accBatchOffset * blockIdx.z;
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auto* addrAcc = MappingAcc::dataCoord(accWithOffset, matrixCoordC, m);
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store_matrix_sync(addrAcc, fragAcc, m, mem_row_major);
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// Copy lower triangular from acc to output
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auto fragColIdx = threadIdx.x % TILE_DIM;
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auto globalColIdx = get<1>(matrixCoordC) + fragColIdx;
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auto rowsPerStep = Constants::AMDGCN_WAVE_SIZE / TILE_DIM;
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count = (TILE_DIM * TILE_DIM) >> Log2<Constants::AMDGCN_WAVE_SIZE>::value;
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for(int i = 0; i < count; i++)
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{
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auto fragRowIdx = i * rowsPerStep
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+ ((threadIdx.x & (Constants::AMDGCN_WAVE_SIZE - 1)) / TILE_DIM);
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auto globalRowIdx = get<0>(matrixCoordC) + fragRowIdx;
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if(globalRowIdx > globalColIdx)
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{
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auto outputOffset = k + ((globalRowIdx * (globalRowIdx - 1)) >> 1);
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output[outputBatchOffset * blockIdx.z + outputOffset + globalColIdx]
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= static_cast<DataT>(
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acc[accBatchOffset * blockIdx.z + globalRowIdx * m + globalColIdx]);
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}
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}
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}
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}
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} // namespace rocwmma
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#endif // DLRM_DOT_FWD_HPP
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