derek.holloway
7502bf64a4
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47 lines
1.8 KiB
ArmAsm
47 lines
1.8 KiB
ArmAsm
# RUN: %stinkytofu-opt --arch gfx1250 %s --emit-asm
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#
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# IRConverter directive round-trip:
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#
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# (a) TEXTBLOCK pass-through: arbitrary text that the parser cannot decode
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# as an instruction (e.g. /* ... */ comment blocks, banner-style
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# comments) is wrapped as an asm_directive with a "TEXTBLOCK" sentinel
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# by RawAsmParser::makeTextBlock. IRConverter must recognize the
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# sentinel and set AsmDirectiveKind::TEXTBLOCK so the emitter prints
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# the text verbatim, instead of letting the kind default to SET (whose
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# emitter concatenates name + symbol and would print
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# "TEXTBLOCK <raw text>").
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#
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# (b) .set value round-trip: RawAsmParser packs `.set` as
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# srcRegs = {".set", symbol, value}. IRConverter must wire srcRegs[2]
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# into AsmDirective::value; otherwise the SET emitter branch (which
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# prints "name symbol[, value]") drops the assignment and a line like
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# ".set vgprValuMXSA_X0_I0_BASE, vgprMXSBase+0" round-trips as the
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# incomplete ".set vgprValuMXSA_X0_I0_BASE".
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#
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# Banner-style and inline /* ... */ comments must appear verbatim with no
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# "TEXTBLOCK" sentinel leaking anywhere into the output.
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#
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# CHECK-NOT: TEXTBLOCK
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# CHECK: /* Mapping of Acc register -> C Vgpr register */
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# CHECK: /******************************************/
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# CHECK: /* Begin Kernel */
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# CHECK: /******************************************/
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# CHECK: .set vgprBase, 0
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# CHECK: .set vgprValuMXSA_X0_I0_BASE, vgprBase+0
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# CHECK: v_mov_b32 v0, v1
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# CHECK-NOT: TEXTBLOCK
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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/* Mapping of Acc register -> C Vgpr register */
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/******************************************/
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/* Begin Kernel */
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/******************************************/
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.set vgprBase, 0
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.set vgprValuMXSA_X0_I0_BASE, vgprBase+0
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v_mov_b32 v0, v1
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s_endpgm
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