derek.holloway
7502bf64a4
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40 lines
1.9 KiB
ArmAsm
40 lines
1.9 KiB
ArmAsm
# RUN: %stinkytofu-opt --arch gfx1250 %s --RemoveWaitAluPass --emit-asm --from-label test_start --to-label test_end
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#
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# RemoveWaitAluPass — setreg(SCHED_MODE) stripping path, exercised via raw
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# assembly because the stir parser does not accept hwreg() destinations.
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#
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# Strip only s_setreg* targeting the DEP_MODE field of SCHED_MODE:
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# hwreg(26, offset=0, size=2) — DEP_MODE {0,1,2} = expert scheduling mode
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# Other SCHED_MODE bit-fields must NOT be stripped:
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# hwreg(26, offset=4, size=1) — DISABLE_XDL_ARB_STALL (back-to-back WMMA hint)
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# Setregs targeting a different hwreg id are preserved unchanged.
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#
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# All s_wait_alu instructions in this region carry only GPR hazard fields,
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# so every one is deleted by the pass.
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#
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# CHECK-LABEL: test_start:
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# DEP_MODE setregs (hwreg(26,0,2)) and all s_wait_alu are stripped.
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# CHECK-NOT: hwreg(26,0,2)
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# CHECK-NOT: s_wait_alu
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# Source ordering of the VALUs plus the kept setregs is preserved.
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# CHECK: v_add_f32
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# CHECK-NEXT: s_setreg_IMM32_b32 hwreg(26,4,1)
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# CHECK-NEXT: v_mul_f32
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# CHECK-NEXT: s_setreg_IMM32_b32 hwreg(1,0,2)
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# CHECK-NEXT: v_sub_f32
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# CHECK-LABEL: test_end:
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test_start:
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s_setreg_IMM32_b32 hwreg(26,0,2), 2 // DEP_MODE = mode2 enable - strip
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s_wait_alu depctr_va_vdst(0) // GPR field only - strip
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v_add_f32 v0, v1, v2
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s_setreg_IMM32_b32 hwreg(26,4,1), 1 // DISABLE_XDL_ARB_STALL - KEEP (WMMA perf hint)
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s_wait_alu depctr_vm_vsrc(0) // GPR field only - strip
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v_mul_f32 v3, v0, v4
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s_setreg_IMM32_b32 hwreg(1,0,2), 3 // MODE register (id=1), unrelated - keep
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s_setreg_IMM32_b32 hwreg(26,0,2), 1 // DEP_MODE = mode1 enable - strip
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s_wait_alu depctr_va_sdst(0) | depctr_va_vdst(0) // GPR fields - strip
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v_sub_f32 v5, v3, v6
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s_setreg_IMM32_b32 hwreg(26,0,2), 0 // DEP_MODE = mode0 disable - strip
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test_end:
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