derek.holloway
7502bf64a4
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142 lines
12 KiB
Plaintext
142 lines
12 KiB
Plaintext
st.func @temp() {
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^entry:
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"st.s_set_vgpr_msb"(0) { issueCycles = 1, latencyCycles = 1 }
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"st.ds_store_b128"(v10, v[50:53]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 0, gds = false } }
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"st.ds_store_b128"(v10, v[54:57]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 2560, gds = false } }
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"st.ds_store_b128"(v11, v[58:61]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 0, gds = false } }
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"st.ds_store_b128"(v11, v[62:65]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 2560, gds = false } }
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"st.s_wait_dscnt"(0) { issueCycles = 1, latencyCycles = 1 }
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"st.s_barrier_signal"(-1) { issueCycles = 1, latencyCycles = 1 }
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"st.s_barrier_wait"(-1) { issueCycles = 1, latencyCycles = 1 }
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v[16:19] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 0, gds = false } }
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v[20:23] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 32, gds = false } }
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v[34:37] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 0, gds = false } }
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v[38:41] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 32, gds = false } }
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Successors: ^label_openLoopL
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^label_openLoopL:
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"st.s_cmp_le_u32"(s0, 0x1) { issueCycles = 1, latencyCycles = 1 }
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"st.s_cbranch_scc1"(label_LoopEndL) { issueCycles = 1, latencyCycles = 1 }
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Successors: ^label_LoopBeginL
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^label_LoopBeginL:
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"st.s_nop"(0) { issueCycles = 1, latencyCycles = 1 }
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"st.s_set_vgpr_msb"(0) { issueCycles = 1, latencyCycles = 1 }
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v[50:53] = "st.buffer_load_b128"(v8, s[0:3], 0) { issueCycles = 12, latencyCycles = 116, mod.mubuf = { offen = true, offset12 = 0, glc = false, slc = false, nt = false, lds = false } }
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v[54:57] = "st.buffer_load_b128"(v8, s[0:3], s0) { issueCycles = 12, latencyCycles = 116, mod.mubuf = { offen = true, offset12 = 0, glc = false, slc = false, nt = false, lds = false } }
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v[58:61] = "st.buffer_load_b128"(v9, s[0:3], 0) { issueCycles = 12, latencyCycles = 116, mod.mubuf = { offen = true, offset12 = 0, glc = false, slc = false, nt = false, lds = false } }
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v[62:65] = "st.buffer_load_b128"(v9, s[0:3], s0) { issueCycles = 12, latencyCycles = 116, mod.mubuf = { offen = true, offset12 = 0, glc = false, slc = false, nt = false, lds = false } }
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SCC0 = "st.s_cmp_eq_u32"(s0, s0) { issueCycles = 1, latencyCycles = 1 }
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s68 = "st.s_cselect_b32"(s0, s0, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s69 = "st.s_cselect_b32"(s1, 0, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s0, SCC0 = "st.s_add_u32"(s0, s68) { issueCycles = 1, latencyCycles = 1 }
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s1, SCC0 = "st.s_addc_u32"(s1, s69) { issueCycles = 1, latencyCycles = 1 }
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s0, SCC0 = "st.s_sub_u32"(s0, s68) { issueCycles = 1, latencyCycles = 1 }
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s1, SCC0 = "st.s_subb_u32"(s1, s69) { issueCycles = 1, latencyCycles = 1 }
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SCC0 = "st.s_cmp_eq_u32"(s1, 0) { issueCycles = 1, latencyCycles = 1 }
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s2 = "st.s_cselect_b32"(s0, BufferLimit, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s8 = "st.s_and_b32"(s2, 127) { issueCycles = 1, latencyCycles = 1 }
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s8 = "st.s_lshl_b32"(s8, 25) { issueCycles = 1, latencyCycles = 1 }
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s1 = "st.s_and_b32"(s1, 33554431) { issueCycles = 1, latencyCycles = 1 }
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s1 = "st.s_or_b32"(s1, s8) { issueCycles = 1, latencyCycles = 1 }
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s2 = "st.s_lshr_b32"(s2, 7) { issueCycles = 1, latencyCycles = 1 }
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SCC0 = "st.s_cmp_eq_u32"(s0, s0) { issueCycles = 1, latencyCycles = 1 }
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s68 = "st.s_cselect_b32"(s0, s0, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s69 = "st.s_cselect_b32"(s1, 0, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s0, SCC0 = "st.s_add_u32"(s0, s68) { issueCycles = 1, latencyCycles = 1 }
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s1, SCC0 = "st.s_addc_u32"(s1, s69) { issueCycles = 1, latencyCycles = 1 }
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s0, SCC0 = "st.s_sub_u32"(s0, s68) { issueCycles = 1, latencyCycles = 1 }
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s1, SCC0 = "st.s_subb_u32"(s1, s69) { issueCycles = 1, latencyCycles = 1 }
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SCC0 = "st.s_cmp_eq_u32"(s1, 0) { issueCycles = 1, latencyCycles = 1 }
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s2 = "st.s_cselect_b32"(s0, BufferLimit, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s8 = "st.s_and_b32"(s2, 127) { issueCycles = 1, latencyCycles = 1 }
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s8 = "st.s_lshl_b32"(s8, 25) { issueCycles = 1, latencyCycles = 1 }
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s1 = "st.s_and_b32"(s1, 33554431) { issueCycles = 1, latencyCycles = 1 }
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s1 = "st.s_or_b32"(s1, s8) { issueCycles = 1, latencyCycles = 1 }
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s2 = "st.s_lshr_b32"(s2, 7) { issueCycles = 1, latencyCycles = 1 }
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v[24:27] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 64, gds = false } }
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v[28:31] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 96, gds = false } }
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v[42:45] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 64, gds = false } }
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v[46:49] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 96, gds = false } }
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"st.s_wait_loadcnt"(0) { issueCycles = 1, latencyCycles = 1 }
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"st.ds_store_b128"(v10, v[50:53]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 16384, gds = false } }
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"st.ds_store_b128"(v10, v[54:57]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 18944, gds = false } }
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"st.ds_store_b128"(v11, v[58:61]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 16384, gds = false } }
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"st.ds_store_b128"(v11, v[62:65]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 18944, gds = false } }
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"st.s_wait_dscnt"(8) { issueCycles = 1, latencyCycles = 1 }
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v[0:7] = "st.v_wmma_f32_16x16x32_bf16"(v[16:23], v[34:41], v[0:7]) { issueCycles = 1, latencyCycles = 16, mod.mfma = { reuseA = false, reuseB = false } }
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"st.s_wait_dscnt"(0) { issueCycles = 1, latencyCycles = 1 }
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"st.s_barrier_signal"(-1) { issueCycles = 1, latencyCycles = 1 }
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"st.s_barrier_wait"(-1) { issueCycles = 1, latencyCycles = 1 }
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v[16:19] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 16384, gds = false } }
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v[20:23] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 16416, gds = false } }
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v[34:37] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 16384, gds = false } }
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v[38:41] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 16416, gds = false } }
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"st.s_wait_dscnt"(8) { issueCycles = 1, latencyCycles = 1 }
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v[0:7] = "st.v_wmma_f32_16x16x32_bf16"(v[24:31], v[42:49], v[0:7]) { issueCycles = 1, latencyCycles = 16, mod.mfma = { reuseA = false, reuseB = false } }
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s0, SCC0 = "st.s_sub_u32"(s0, 1) { issueCycles = 1, latencyCycles = 1 }
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SCC0 = "st.s_cmp_eq_i32"(s0, 0x1) { issueCycles = 1, latencyCycles = 1 }
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"st.s_cbranch_scc1"(label_LoopEndL_oddexit) { issueCycles = 1, latencyCycles = 1 }
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v[50:53] = "st.buffer_load_b128"(v8, s[0:3], 0) { issueCycles = 12, latencyCycles = 116, mod.mubuf = { offen = true, offset12 = 0, glc = false, slc = false, nt = false, lds = false } }
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v[54:57] = "st.buffer_load_b128"(v8, s[0:3], s0) { issueCycles = 12, latencyCycles = 116, mod.mubuf = { offen = true, offset12 = 0, glc = false, slc = false, nt = false, lds = false } }
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v[58:61] = "st.buffer_load_b128"(v9, s[0:3], 0) { issueCycles = 12, latencyCycles = 116, mod.mubuf = { offen = true, offset12 = 0, glc = false, slc = false, nt = false, lds = false } }
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v[62:65] = "st.buffer_load_b128"(v9, s[0:3], s0) { issueCycles = 12, latencyCycles = 116, mod.mubuf = { offen = true, offset12 = 0, glc = false, slc = false, nt = false, lds = false } }
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SCC0 = "st.s_cmp_eq_u32"(s0, s0) { issueCycles = 1, latencyCycles = 1 }
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s68 = "st.s_cselect_b32"(s0, s0, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s69 = "st.s_cselect_b32"(s1, 0, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s0, SCC0 = "st.s_add_u32"(s0, s68) { issueCycles = 1, latencyCycles = 1 }
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s1, SCC0 = "st.s_addc_u32"(s1, s69) { issueCycles = 1, latencyCycles = 1 }
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s0, SCC0 = "st.s_sub_u32"(s0, s68) { issueCycles = 1, latencyCycles = 1 }
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s1, SCC0 = "st.s_subb_u32"(s1, s69) { issueCycles = 1, latencyCycles = 1 }
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SCC0 = "st.s_cmp_eq_u32"(s1, 0) { issueCycles = 1, latencyCycles = 1 }
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s2 = "st.s_cselect_b32"(s0, BufferLimit, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s8 = "st.s_and_b32"(s2, 127) { issueCycles = 1, latencyCycles = 1 }
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s8 = "st.s_lshl_b32"(s8, 25) { issueCycles = 1, latencyCycles = 1 }
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s1 = "st.s_and_b32"(s1, 33554431) { issueCycles = 1, latencyCycles = 1 }
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s1 = "st.s_or_b32"(s1, s8) { issueCycles = 1, latencyCycles = 1 }
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s2 = "st.s_lshr_b32"(s2, 7) { issueCycles = 1, latencyCycles = 1 }
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SCC0 = "st.s_cmp_eq_u32"(s0, s0) { issueCycles = 1, latencyCycles = 1 }
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s68 = "st.s_cselect_b32"(s0, s0, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s69 = "st.s_cselect_b32"(s1, 0, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s0, SCC0 = "st.s_add_u32"(s0, s68) { issueCycles = 1, latencyCycles = 1 }
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s1, SCC0 = "st.s_addc_u32"(s1, s69) { issueCycles = 1, latencyCycles = 1 }
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s0, SCC0 = "st.s_sub_u32"(s0, s68) { issueCycles = 1, latencyCycles = 1 }
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s1, SCC0 = "st.s_subb_u32"(s1, s69) { issueCycles = 1, latencyCycles = 1 }
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SCC0 = "st.s_cmp_eq_u32"(s1, 0) { issueCycles = 1, latencyCycles = 1 }
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s2 = "st.s_cselect_b32"(s0, BufferLimit, SCC0) { issueCycles = 1, latencyCycles = 1 }
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s8 = "st.s_and_b32"(s2, 127) { issueCycles = 1, latencyCycles = 1 }
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s8 = "st.s_lshl_b32"(s8, 25) { issueCycles = 1, latencyCycles = 1 }
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s1 = "st.s_and_b32"(s1, 33554431) { issueCycles = 1, latencyCycles = 1 }
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s1 = "st.s_or_b32"(s1, s8) { issueCycles = 1, latencyCycles = 1 }
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s2 = "st.s_lshr_b32"(s2, 7) { issueCycles = 1, latencyCycles = 1 }
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v[24:27] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 16448, gds = false } }
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v[28:31] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 16480, gds = false } }
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v[42:45] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 16448, gds = false } }
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v[46:49] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 16480, gds = false } }
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"st.s_wait_loadcnt"(0) { issueCycles = 1, latencyCycles = 1 }
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"st.ds_store_b128"(v10, v[50:53]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 0, gds = false } }
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"st.ds_store_b128"(v10, v[54:57]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 2560, gds = false } }
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"st.ds_store_b128"(v11, v[58:61]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 0, gds = false } }
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"st.ds_store_b128"(v11, v[62:65]) { issueCycles = 1, latencyCycles = 1, mod.ds = { na = 1, offset = 2560, gds = false } }
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"st.s_wait_dscnt"(8) { issueCycles = 1, latencyCycles = 1 }
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v[0:7] = "st.v_wmma_f32_16x16x32_bf16"(v[16:23], v[34:41], v[0:7]) { issueCycles = 1, latencyCycles = 16, mod.mfma = { reuseA = false, reuseB = false } }
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"st.s_wait_dscnt"(0) { issueCycles = 1, latencyCycles = 1 }
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"st.s_barrier_signal"(-1) { issueCycles = 1, latencyCycles = 1 }
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"st.s_barrier_wait"(-1) { issueCycles = 1, latencyCycles = 1 }
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v[16:19] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 0, gds = false } }
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v[20:23] = "st.ds_load_b128"(v12) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 32, gds = false } }
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v[34:37] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 0, gds = false } }
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v[38:41] = "st.ds_load_b128"(v13) { issueCycles = 1, latencyCycles = 56, mod.ds = { na = 1, offset = 32, gds = false } }
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"st.s_wait_dscnt"(8) { issueCycles = 1, latencyCycles = 1 }
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v[0:7] = "st.v_wmma_f32_16x16x32_bf16"(v[24:31], v[42:49], v[0:7]) { issueCycles = 1, latencyCycles = 16, mod.mfma = { reuseA = false, reuseB = false } }
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s0, SCC0 = "st.s_sub_u32"(s0, 1) { issueCycles = 1, latencyCycles = 1 }
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SCC0 = "st.s_cmp_eq_i32"(s0, 0x1) { issueCycles = 1, latencyCycles = 1 }
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"st.s_cbranch_scc0"(label_LoopBeginL) { issueCycles = 1, latencyCycles = 1 }
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Successors: ^label_LoopBeginL, ^label_LoopEndL_evenexit
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^label_LoopEndL_evenexit:
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"st.s_branch"(label_LoopEndL) { issueCycles = 1, latencyCycles = 1 }
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^label_LoopEndL_oddexit:
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"st.s_nop"(0) { issueCycles = 1, latencyCycles = 1 }
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"st.s_set_vgpr_msb"(0) { issueCycles = 1, latencyCycles = 1 }
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v12 = "st.v_xor_b32"(0x4000, v12) { issueCycles = 1, latencyCycles = 1 }
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v13 = "st.v_xor_b32"(0x4000, v13) { issueCycles = 1, latencyCycles = 1 }
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}
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