derek.holloway
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47 lines
1.2 KiB
C++
47 lines
1.2 KiB
C++
/*
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* Copyright (c) Advanced Micro Devices, Inc., or its affiliates.
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*
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* SPDX-License-Identifier: MIT
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*/
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#pragma once
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namespace amd::roc {
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//! Alignment restriction for the pinned memory
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static constexpr size_t PinnedMemoryAlignment = 4 * Ki;
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//! Specific defines for images for Dynamic Parallelism
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static constexpr uint DeviceQueueMaskSize = 32;
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//! Set to match the number of pipes, which is 8.
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static constexpr uint kMaxAsyncQueues = 8;
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constexpr bool kSkipCpuWait = true;
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enum HwQueueEngine : uint32_t {
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Compute = 0,
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SdmaD2H = 1,
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SdmaH2D = 2,
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SdmaD2D = 3,
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SdmaP2P = 4,
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Unknown = 5
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};
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//! Returns true if the engine is an SDMA engine (any type)
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inline bool IsSdmaEngine(HwQueueEngine engine) {
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return engine >= HwQueueEngine::SdmaD2H && engine <= HwQueueEngine::SdmaP2P;
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}
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inline const char* EngineOpName(HwQueueEngine engine) {
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switch (engine) {
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case HwQueueEngine::SdmaD2H: return "D2H";
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case HwQueueEngine::SdmaH2D: return "H2D";
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case HwQueueEngine::SdmaD2D:
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case HwQueueEngine::SdmaP2P: return "D2D/P2P";
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case HwQueueEngine::Compute: return "Compute";
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default: return "Unknown";
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}
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}
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} // namespace amd::roc
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