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112 lines
4.0 KiB
C++
112 lines
4.0 KiB
C++
#if !defined(SG_ASM_X86_INSN_H)
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#define SG_ASM_X86_INSN_H
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// This information is cut from a generated SAGEIII file.
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// Since we only need the data structure definition I've
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// extracted that from the larger generated file.
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// All methods that do not appear to be used by x86InstructionSemantics.h
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// have been commented out.
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#include <stdint.h>
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#include <string>
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#include "external/rose/rose-compat.h"
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#include "typedefs.h"
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#include "SgAsmInstruction.h"
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class SgAsmx86Instruction : public SgAsmInstruction {
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public:
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/*! \brief returns a string representing the class name */
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virtual std::string class_name() const;
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/*! \brief returns new style SageIII enum values */
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virtual VariantT variantT() const; // MS: new variant used in tree traversal
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/*! \brief static variant value */
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static const VariantT static_variant = V_SgAsmx86Instruction;
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/* the generated cast function */
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/*! \brief Casts pointer from base class to derived class */
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friend SgAsmx86Instruction* isSgAsmx86Instruction( SgNode * s );
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/*! \brief Casts pointer from base class to derived class (for const pointers) */
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friend const SgAsmx86Instruction* isSgAsmx86Instruction( const SgNode * s );
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X86InstructionKind get_kind() const;
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void set_kind(X86InstructionKind kind);
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X86InstructionSize get_baseSize() const;
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void set_baseSize(X86InstructionSize baseSize);
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X86InstructionSize get_operandSize() const;
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void set_operandSize(X86InstructionSize operandSize);
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X86InstructionSize get_addressSize() const;
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void set_addressSize(X86InstructionSize addressSize);
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bool get_lockPrefix() const;
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void set_lockPrefix(bool lockPrefix);
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X86RepeatPrefix get_repeatPrefix() const;
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void set_repeatPrefix(X86RepeatPrefix repeatPrefix);
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X86BranchPrediction get_branchPrediction() const;
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void set_branchPrediction(X86BranchPrediction branchPrediction);
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X86SegmentRegister get_segmentOverride() const;
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void set_segmentOverride(X86SegmentRegister segmentOverride);
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virtual ~SgAsmx86Instruction();
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SgAsmx86Instruction(rose_addr_t address = 0,
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std::string mnemonic = "",
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X86InstructionKind kind = x86_unknown_instruction,
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X86InstructionSize baseSize = x86_insnsize_none,
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X86InstructionSize operandSize = x86_insnsize_none,
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X86InstructionSize addressSize = x86_insnsize_none);
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protected:
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X86InstructionKind p_kind;
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X86InstructionSize p_baseSize;
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X86InstructionSize p_operandSize;
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X86InstructionSize p_addressSize;
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bool p_lockPrefix;
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X86RepeatPrefix p_repeatPrefix;
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X86BranchPrediction p_branchPrediction;
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X86SegmentRegister p_segmentOverride;
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// End of memberFunctionString
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};
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// from src/frontend/BinaryDisassembly/x86InstructionProperties.h
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bool x86InstructionIsConditionalFlagControlTransfer(SgAsmx86Instruction* inst);
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bool x86InstructionIsConditionalFlagDataTransfer(SgAsmx86Instruction* inst);
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bool x86InstructionIsConditionalControlTransfer(SgAsmx86Instruction* inst);
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bool x86InstructionIsConditionalDataTransfer(SgAsmx86Instruction* inst);
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bool x86InstructionIsConditionalFlagBitAndByte(SgAsmx86Instruction* inst);
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bool x86InstructionIsControlTransfer(SgAsmx86Instruction* inst);
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bool x86InstructionIsUnconditionalBranch(SgAsmx86Instruction* inst);
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bool x86InstructionIsConditionalBranch(SgAsmx86Instruction* inst);
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bool x86InstructionIsDataTransfer(SgAsmx86Instruction* inst);
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bool x86GetKnownBranchTarget(SgAsmx86Instruction* insn, uint64_t& addr);
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// SgAsmx86Instruction* x86GetInstructionDestination(SgAsmx86Instruction* inst); // Returns non-fallthrough destination
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// std::vector<SgAsmx86Instruction*> x86GetInstructionOutEdges(SgAsmx86Instruction* inst); // Returns all possible targets and fallthrough
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const char* regclassToString(X86RegisterClass n);
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const char* gprToString(X86GeneralPurposeRegister n);
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const char* segregToString(X86SegmentRegister n);
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const char* flagToString(X86Flag n);
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#endif
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