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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=riscv32 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s
---
name: freeze_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: freeze_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
; CHECK-NEXT: $x10 = COPY [[FREEZE]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%2:_(s32) = G_FREEZE %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...
---
name: freeze_f32
body: |
bb.0.entry:
; CHECK-LABEL: name: freeze_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%1:_(s32) = COPY $f10_f
%2:_(s32) = G_FREEZE %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f
...
---
name: freeze_nxv2i1
body: |
bb.0.entry:
; CHECK-LABEL: name: freeze_nxv2i1
; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s1>) = G_FREEZE [[COPY]]
; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s1>) = COPY $v8
%2:_(<vscale x 2 x s1>) = G_FREEZE %1
$v8 = COPY %2(<vscale x 2 x s1>)
PseudoRET implicit $v8
...
---
name: freeze_nxv2i32
body: |
bb.0.entry:
; CHECK-LABEL: name: freeze_nxv2i32
; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s32>) = G_FREEZE [[COPY]]
; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s32>) = COPY $v8
%2:_(<vscale x 2 x s32>) = G_FREEZE %1
$v8 = COPY %2(<vscale x 2 x s32>)
PseudoRET implicit $v8
...