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288 lines
8.5 KiB
C++
288 lines
8.5 KiB
C++
// Copyright Advanced Micro Devices, Inc., or its affiliates.
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// SPDX-License-Identifier: MIT
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#include <rocRoller/GPUArchitecture/GPUInstructionInfo.hpp>
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#include <rocRoller/Utilities/Error.hpp>
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#include <rocRoller/Utilities/Settings.hpp>
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namespace rocRoller
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{
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bool GPUInstructionInfo::isDLOP(std::string const& opCode)
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{
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return opCode.starts_with("v_dot");
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}
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bool GPUInstructionInfo::isMFMA(std::string const& opCode)
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{
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return opCode.starts_with("v_mfma");
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}
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bool GPUInstructionInfo::isWMMA(std::string const& opCode)
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{
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return opCode.starts_with("v_wmma");
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}
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bool GPUInstructionInfo::isSWMMAC(std::string const& opCode)
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{
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return opCode.rfind("v_swmmac", 0) == 0;
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}
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bool GPUInstructionInfo::isVCMPX(std::string const& opCode)
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{
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return opCode.starts_with("v_cmpx_");
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}
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bool GPUInstructionInfo::isVCMP(std::string const& opCode)
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{
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return opCode.starts_with("v_cmp_");
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}
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bool GPUInstructionInfo::isScalar(std::string const& opCode)
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{
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return opCode.starts_with("s_");
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}
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bool GPUInstructionInfo::isSMEM(std::string const& opCode)
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{
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return opCode.starts_with("s_load") || opCode.starts_with("s_store");
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}
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bool GPUInstructionInfo::isSBarrier(std::string const& opCode)
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{
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return opCode.starts_with("s_barrier");
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}
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bool GPUInstructionInfo::isSControl(std::string const& opCode)
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{
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return isScalar(opCode)
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&& (opCode.find("branch") != std::string::npos //
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|| opCode == "s_endpgm" || isSBarrier(opCode));
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}
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bool GPUInstructionInfo::isSALU(std::string const& opCode)
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{
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return isScalar(opCode) && !isSMEM(opCode) && !isSControl(opCode);
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}
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bool GPUInstructionInfo::isVector(std::string const& opCode)
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{
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return (opCode.starts_with("v_")) || isVMEM(opCode) || isFlat(opCode) || isLDS(opCode);
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}
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bool GPUInstructionInfo::isVALU(std::string const& opCode)
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{
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return isVector(opCode) && !isVMEM(opCode) && !isFlat(opCode) && !isLDS(opCode)
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&& !isMFMA(opCode) && !isDLOP(opCode);
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}
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bool GPUInstructionInfo::isVALUTrans(std::string const& opCode)
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{
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return isVALU(opCode)
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&& (opCode.starts_with("v_exp_f32") || opCode.starts_with("v_log_f32")
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|| opCode.starts_with("v_rcp_f32") || opCode.starts_with("v_rcp_iflag_f32")
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|| opCode.starts_with("v_rsq_f32") || opCode.starts_with("v_rcp_f64")
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|| opCode.starts_with("v_rsq_f64") || opCode.starts_with("v_sqrt_f32")
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|| opCode.starts_with("v_sqrt_f64") || opCode.starts_with("v_sin_f32")
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|| opCode.starts_with("v_cos_f32") || opCode.starts_with("v_rcp_f16")
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|| opCode.starts_with("v_sqrt_f16") || opCode.starts_with("v_rsq_f16")
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|| opCode.starts_with("v_log_f16") || opCode.starts_with("v_exp_f16")
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|| opCode.starts_with("v_sin_f16") || opCode.starts_with("v_cos_f16")
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|| opCode.starts_with("v_exp_legacy_f32")
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|| opCode.starts_with("v_log_legacy_f32"));
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}
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bool GPUInstructionInfo::isDGEMM(std::string const& opCode)
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{
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return opCode.starts_with("v_mfma_f64");
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}
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bool GPUInstructionInfo::isSGEMM(std::string const& opCode)
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{
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auto endPos = opCode.length() - 4;
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return opCode.starts_with("v_mfma_") && opCode.rfind("f32", endPos) == 0;
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}
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bool GPUInstructionInfo::isVMEM(std::string const& opCode)
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{
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return opCode.starts_with("buffer_") || opCode.starts_with("global_");
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}
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bool GPUInstructionInfo::isVMEMRead(std::string const& opCode)
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{
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return isVMEM(opCode)
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&& (opCode.find("read") != std::string::npos
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|| opCode.find("load") != std::string::npos);
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}
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bool GPUInstructionInfo::isVMEMWrite(std::string const& opCode)
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{
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return isVMEM(opCode)
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&& (opCode.find("write") != std::string::npos
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|| opCode.find("store") != std::string::npos);
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}
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bool GPUInstructionInfo::isFlat(std::string const& opCode)
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{
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return opCode.starts_with("flat_");
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}
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bool GPUInstructionInfo::isLDS(std::string const& opCode)
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{
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return opCode.starts_with("ds_");
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}
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bool GPUInstructionInfo::isLDSRead(std::string const& opCode)
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{
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return isLDS(opCode)
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&& (opCode.find("read") != std::string::npos
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|| opCode.find("load") != std::string::npos);
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}
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bool GPUInstructionInfo::isLDSWrite(std::string const& opCode)
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{
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return isLDS(opCode)
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&& (opCode.find("write") != std::string::npos
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|| opCode.find("store") != std::string::npos);
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}
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bool GPUInstructionInfo::isTensor(std::string const& opCode)
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{
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return opCode.starts_with("tensor_");
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}
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bool GPUInstructionInfo::isACCVGPRWrite(std::string const& opCode)
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{
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return opCode.starts_with("v_accvgpr_write");
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}
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bool GPUInstructionInfo::isACCVGPRRead(std::string const& opCode)
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{
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return opCode.starts_with("v_accvgpr_read");
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}
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bool GPUInstructionInfo::isIntInst(std::string const& opCode)
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{
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return opCode.find("_i32") != std::string::npos || opCode.find("_i64") != std::string::npos;
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}
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bool GPUInstructionInfo::isUIntInst(std::string const& opCode)
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{
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return opCode.find("_u32") != std::string::npos || opCode.find("_u64") != std::string::npos;
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}
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bool GPUInstructionInfo::isVAddInst(std::string const& opCode)
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{
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return opCode.starts_with("v_add");
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}
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bool GPUInstructionInfo::isVAddCarryInst(std::string const& opCode)
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{
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return opCode.starts_with("v_addc_");
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}
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bool GPUInstructionInfo::isVSubInst(std::string const& opCode)
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{
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return opCode.starts_with("v_sub");
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}
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bool GPUInstructionInfo::isVSubCarryInst(std::string const& opCode)
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{
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return opCode.starts_with("v_subb_");
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}
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bool GPUInstructionInfo::isVReadlane(std::string const& opCode)
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{
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return opCode.starts_with("v_readlane") || opCode.starts_with("v_readfirstlane");
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}
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bool GPUInstructionInfo::isVWritelane(std::string const& opCode)
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{
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return opCode.starts_with("v_writelane");
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}
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bool GPUInstructionInfo::isVPermlane(std::string const& opCode)
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{
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return opCode.starts_with("v_permlane");
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}
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bool GPUInstructionInfo::isVDivScale(std::string const& opCode)
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{
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return opCode.starts_with("v_div_scale");
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}
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bool GPUInstructionInfo::isVDivFmas(std::string const& opCode)
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{
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return opCode.starts_with("v_div_fmas_");
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}
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CoexecCategory GPUInstructionInfo::getCoexecCategory(std::string const& opCode)
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{
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if(opCode.empty())
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return CoexecCategory::NotAnInstruction;
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if(isScalar(opCode))
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return CoexecCategory::Scalar;
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if(isMFMA(opCode))
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{
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if(opCode.find("scale") != std::string::npos)
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return CoexecCategory::XDL_Scale;
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return CoexecCategory::XDL;
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}
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if(isDLOP(opCode))
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return CoexecCategory::XDL;
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if(isVALUTrans(opCode))
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return CoexecCategory::VALU_Trans;
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if(isVALU(opCode))
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return CoexecCategory::VALU;
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if(isVMEM(opCode) || isFlat(opCode))
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return CoexecCategory::VMEM;
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if(isLDS(opCode) || isTensor(opCode))
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return CoexecCategory::LDS;
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if(Settings::Get(Settings::AllowUnknownInstructions))
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{
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return CoexecCategory::NotAnInstruction;
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}
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else
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{
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Throw<FatalError>("Unknown category for ", ShowValue(opCode));
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}
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return CoexecCategory::Count;
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}
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std::string toString(CoexecCategory cat)
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{
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switch(cat)
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{
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case CoexecCategory::NotAnInstruction:
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return "NotAnInstruction";
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case CoexecCategory::Scalar:
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return "Scalar";
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case CoexecCategory::VMEM:
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return "VMEM";
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case CoexecCategory::VALU:
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return "VALU";
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case CoexecCategory::VALU_Trans:
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return "VALU_Trans";
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case CoexecCategory::XDL:
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return "XDL";
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case CoexecCategory::XDL_Scale:
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return "XDL_Scale";
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case CoexecCategory::LDS:
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return "LDS";
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case CoexecCategory::Count:
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break;
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}
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return "Invalid Category";
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}
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}
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