derek.holloway
7502bf64a4
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211 lines
10 KiB
LLVM
211 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-late-codegenprepare %s | FileCheck %s -check-prefix=GFX9
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -amdgpu-late-codegenprepare %s | FileCheck %s -check-prefix=GFX12
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-late-codegenprepare %s | FileCheck %s -check-prefix=GFX9
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; Make sure we don't crash when trying to create a bitcast between
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; address spaces
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define amdgpu_kernel void @constant_from_offset_cast_generic_null() {
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; GFX9-LABEL: @constant_from_offset_cast_generic_null(
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; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4)), i64 4), align 4
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; GFX9-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; GFX9-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; GFX9-NEXT: store i8 [[TMP3]], ptr addrspace(1) poison, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_offset_cast_generic_null(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4)), i64 6), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) poison, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4)), i64 6), align 1
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store i8 %load, ptr addrspace(1) poison
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ret void
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}
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define amdgpu_kernel void @constant_from_offset_cast_global_null() {
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; GFX9-LABEL: @constant_from_offset_cast_global_null(
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; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4)), i64 4), align 4
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; GFX9-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; GFX9-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; GFX9-NEXT: store i8 [[TMP3]], ptr addrspace(1) poison, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_offset_cast_global_null(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4)), i64 6), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) poison, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4)), i64 6), align 1
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store i8 %load, ptr addrspace(1) poison
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ret void
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}
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@gv = unnamed_addr addrspace(1) global [64 x i8] poison, align 4
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define amdgpu_kernel void @constant_from_offset_cast_global_gv() {
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; GFX9-LABEL: @constant_from_offset_cast_global_gv(
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; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) @gv to ptr addrspace(4)), i64 4), align 4
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; GFX9-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; GFX9-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; GFX9-NEXT: store i8 [[TMP3]], ptr addrspace(1) poison, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_offset_cast_global_gv(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) @gv to ptr addrspace(4)), i64 6), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) poison, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) @gv to ptr addrspace(4)), i64 6), align 1
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store i8 %load, ptr addrspace(1) poison
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ret void
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}
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define amdgpu_kernel void @constant_from_offset_cast_generic_inttoptr() {
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; GFX9-LABEL: @constant_from_offset_cast_generic_inttoptr(
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; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr inttoptr (i64 128 to ptr) to ptr addrspace(4)), i64 4), align 4
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; GFX9-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; GFX9-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; GFX9-NEXT: store i8 [[TMP3]], ptr addrspace(1) poison, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_offset_cast_generic_inttoptr(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr inttoptr (i64 128 to ptr) to ptr addrspace(4)), i64 6), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) poison, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr inttoptr (i64 128 to ptr) to ptr addrspace(4)), i64 6), align 1
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store i8 %load, ptr addrspace(1) poison
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ret void
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}
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define amdgpu_kernel void @constant_from_inttoptr() {
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; GFX9-LABEL: @constant_from_inttoptr(
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; GFX9-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) inttoptr (i64 128 to ptr addrspace(4)), align 4
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; GFX9-NEXT: store i8 [[LOAD]], ptr addrspace(1) poison, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_inttoptr(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) inttoptr (i64 128 to ptr addrspace(4)), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) poison, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) inttoptr (i64 128 to ptr addrspace(4)), align 1
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store i8 %load, ptr addrspace(1) poison
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ret void
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}
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define void @broken_phi() {
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; GFX9-LABEL: @broken_phi(
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; GFX9-NEXT: bb:
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; GFX9-NEXT: br label [[BB1:%.*]]
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; GFX9: bb1:
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; GFX9-NEXT: [[I:%.*]] = phi <4 x i8> [ splat (i8 1), [[BB:%.*]] ], [ [[I8:%.*]], [[BB7:%.*]] ]
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; GFX9-NEXT: br i1 false, label [[BB3:%.*]], label [[BB2:%.*]]
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; GFX9: bb2:
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; GFX9-NEXT: br label [[BB3]]
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; GFX9: bb3:
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; GFX9-NEXT: [[I4:%.*]] = phi <4 x i8> [ zeroinitializer, [[BB2]] ], [ [[I]], [[BB1]] ]
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; GFX9-NEXT: br i1 false, label [[BB7]], label [[BB5:%.*]]
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; GFX9: bb5:
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; GFX9-NEXT: [[I6:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[I4]], <4 x i8> zeroinitializer)
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; GFX9-NEXT: br label [[BB7]]
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; GFX9: bb7:
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; GFX9-NEXT: [[I8]] = phi <4 x i8> [ zeroinitializer, [[BB5]] ], [ zeroinitializer, [[BB3]] ]
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; GFX9-NEXT: br label [[BB1]]
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;
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; GFX12-LABEL: @broken_phi(
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; GFX12-NEXT: bb:
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; GFX12-NEXT: br label [[BB1:%.*]]
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; GFX12: bb1:
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; GFX12-NEXT: [[I:%.*]] = phi <4 x i8> [ splat (i8 1), [[BB:%.*]] ], [ [[I8:%.*]], [[BB7:%.*]] ]
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; GFX12-NEXT: br i1 false, label [[BB3:%.*]], label [[BB2:%.*]]
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; GFX12: bb2:
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; GFX12-NEXT: br label [[BB3]]
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; GFX12: bb3:
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; GFX12-NEXT: [[I4:%.*]] = phi <4 x i8> [ zeroinitializer, [[BB2]] ], [ [[I]], [[BB1]] ]
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; GFX12-NEXT: br i1 false, label [[BB7]], label [[BB5:%.*]]
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; GFX12: bb5:
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; GFX12-NEXT: [[I6:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[I4]], <4 x i8> zeroinitializer)
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; GFX12-NEXT: br label [[BB7]]
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; GFX12: bb7:
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; GFX12-NEXT: [[I8]] = phi <4 x i8> [ zeroinitializer, [[BB5]] ], [ zeroinitializer, [[BB3]] ]
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; GFX12-NEXT: br label [[BB1]]
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;
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bb:
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br label %bb1
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bb1:
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%i = phi <4 x i8> [ <i8 1, i8 1, i8 1, i8 1>, %bb ], [ %i8, %bb7 ]
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br i1 false, label %bb3, label %bb2
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bb2:
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br label %bb3
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bb3:
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%i4 = phi <4 x i8> [ zeroinitializer, %bb2 ], [ %i, %bb1 ]
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br i1 false, label %bb7, label %bb5
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bb5:
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%i6 = call <4 x i8> @llvm.smax.v4i8(<4 x i8> %i4, <4 x i8> zeroinitializer)
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br label %bb7
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bb7:
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%i8 = phi <4 x i8> [ zeroinitializer, %bb5 ], [ zeroinitializer, %bb3 ]
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br label %bb1
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}
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; The widened i32 load reads bytes outside the original i8 load, so !noundef
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; must not be carried over for GFX9.
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define amdgpu_kernel void @no_widen_noundef(ptr addrspace(4) align 4 %p, ptr addrspace(1) %out) {
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; GFX9-LABEL: @no_widen_noundef(
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; GFX9-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[P:%.*]], i64 0
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; GFX9-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 4
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; GFX9-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 8
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; GFX9-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8
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; GFX9-NEXT: [[VZ:%.*]] = zext i8 [[TMP4]] to i32
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; GFX9-NEXT: store i32 [[VZ]], ptr addrspace(1) [[OUT:%.*]], align 4
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @no_widen_noundef(
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; GFX12-NEXT: [[P1:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[P:%.*]], i64 1
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; GFX12-NEXT: [[V:%.*]] = load i8, ptr addrspace(4) [[P1]], align 1, !noundef [[META0:![0-9]+]]
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; GFX12-NEXT: [[VZ:%.*]] = zext i8 [[V]] to i32
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; GFX12-NEXT: store i32 [[VZ]], ptr addrspace(1) [[OUT:%.*]], align 4
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; GFX12-NEXT: ret void
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;
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%p1 = getelementptr inbounds i8, ptr addrspace(4) %p, i64 1
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%v = load i8, ptr addrspace(4) %p1, align 1, !noundef !0
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%vz = zext i8 %v to i32
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store i32 %vz, ptr addrspace(1) %out, align 4
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ret void
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}
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; The widened i32 load reads bytes outside the original f16 load, so !nofpclass
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; must not be carried over for GFX9.
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define amdgpu_kernel void @no_widen_nofpclass(ptr addrspace(4) align 4 %p, ptr addrspace(1) %out) {
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; GFX9-LABEL: @no_widen_nofpclass(
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; GFX9-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[P:%.*]], i64 0
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; GFX9-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 4
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; GFX9-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 16
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; GFX9-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
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; GFX9-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP4]] to half
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; GFX9-NEXT: [[VB:%.*]] = bitcast half [[TMP5]] to i16
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; GFX9-NEXT: [[VZ:%.*]] = zext i16 [[VB]] to i32
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; GFX9-NEXT: store i32 [[VZ]], ptr addrspace(1) [[OUT:%.*]], align 4
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @no_widen_nofpclass(
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; GFX12-NEXT: [[P1:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[P:%.*]], i64 2
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; GFX12-NEXT: [[V:%.*]] = load half, ptr addrspace(4) [[P1]], align 2, !nofpclass [[META1:![0-9]+]]
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; GFX12-NEXT: [[VB:%.*]] = bitcast half [[V]] to i16
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; GFX12-NEXT: [[VZ:%.*]] = zext i16 [[VB]] to i32
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; GFX12-NEXT: store i32 [[VZ]], ptr addrspace(1) [[OUT:%.*]], align 4
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; GFX12-NEXT: ret void
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;
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%p1 = getelementptr inbounds i8, ptr addrspace(4) %p, i64 2
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%v = load half, ptr addrspace(4) %p1, align 2, !nofpclass !1
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%vb = bitcast half %v to i16
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%vz = zext i16 %vb to i32
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store i32 %vz, ptr addrspace(1) %out, align 4
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ret void
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}
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!0 = !{}
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!1 = !{i32 3}
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