derek.holloway
7502bf64a4
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108 lines
4.0 KiB
LLVM
108 lines
4.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --enable-var-scope --check-prefix=GCN %s
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; Check that vectorizer does not create slow misaligned loads
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; GCN-LABEL: {{^}}ds1align1:
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; GCN-COUNT-2: ds_read_u8
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; GCN-COUNT-2: ds_write_b8
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define amdgpu_kernel void @ds1align1(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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%val1 = load i8, ptr addrspace(3) %in, align 1
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%gep1 = getelementptr i8, ptr addrspace(3) %in, i32 1
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%val2 = load i8, ptr addrspace(3) %gep1, align 1
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store i8 %val1, ptr addrspace(3) %out, align 1
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%gep2 = getelementptr i8, ptr addrspace(3) %out, i32 1
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store i8 %val2, ptr addrspace(3) %gep2, align 1
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ret void
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}
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; GCN-LABEL: {{^}}ds2align2:
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; GCN-COUNT-2: ds_read_u16
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; GCN-COUNT-2: ds_write_b16
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define amdgpu_kernel void @ds2align2(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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%val1 = load i16, ptr addrspace(3) %in, align 2
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%gep1 = getelementptr i16, ptr addrspace(3) %in, i32 1
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%val2 = load i16, ptr addrspace(3) %gep1, align 2
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store i16 %val1, ptr addrspace(3) %out, align 2
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%gep2 = getelementptr i16, ptr addrspace(3) %out, i32 1
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store i16 %val2, ptr addrspace(3) %gep2, align 2
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ret void
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}
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; GCN-LABEL: {{^}}ds4align4:
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; GCN: ds_read2_b32
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; GCN: ds_write2_b32
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define amdgpu_kernel void @ds4align4(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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%val1 = load i32, ptr addrspace(3) %in, align 4
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%gep1 = getelementptr i32, ptr addrspace(3) %in, i32 1
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%val2 = load i32, ptr addrspace(3) %gep1, align 4
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store i32 %val1, ptr addrspace(3) %out, align 4
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%gep2 = getelementptr i32, ptr addrspace(3) %out, i32 1
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store i32 %val2, ptr addrspace(3) %gep2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}ds8align8:
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; GCN: ds_read2_b64
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; GCN: ds_write2_b64
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define amdgpu_kernel void @ds8align8(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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%val1 = load i64, ptr addrspace(3) %in, align 8
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%gep1 = getelementptr i64, ptr addrspace(3) %in, i64 1
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%val2 = load i64, ptr addrspace(3) %gep1, align 8
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store i64 %val1, ptr addrspace(3) %out, align 8
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%gep2 = getelementptr i64, ptr addrspace(3) %out, i64 1
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store i64 %val2, ptr addrspace(3) %gep2, align 8
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ret void
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}
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; GCN-LABEL: {{^}}ds1align2:
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; GCN: ds_read_u16
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; GCN: ds_write_b16
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define amdgpu_kernel void @ds1align2(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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%val1 = load i8, ptr addrspace(3) %in, align 2
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%gep1 = getelementptr i8, ptr addrspace(3) %in, i32 1
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%val2 = load i8, ptr addrspace(3) %gep1, align 2
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store i8 %val1, ptr addrspace(3) %out, align 2
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%gep2 = getelementptr i8, ptr addrspace(3) %out, i32 1
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store i8 %val2, ptr addrspace(3) %gep2, align 2
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ret void
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}
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; GCN-LABEL: {{^}}ds2align4:
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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define amdgpu_kernel void @ds2align4(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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%val1 = load i16, ptr addrspace(3) %in, align 4
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%gep1 = getelementptr i16, ptr addrspace(3) %in, i32 1
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%val2 = load i16, ptr addrspace(3) %gep1, align 4
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store i16 %val1, ptr addrspace(3) %out, align 4
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%gep2 = getelementptr i16, ptr addrspace(3) %out, i32 1
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store i16 %val2, ptr addrspace(3) %gep2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}ds4align8:
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; GCN: ds_read_b64
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; GCN: ds_write_b64
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define amdgpu_kernel void @ds4align8(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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%val1 = load i32, ptr addrspace(3) %in, align 8
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%gep1 = getelementptr i32, ptr addrspace(3) %in, i32 1
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%val2 = load i32, ptr addrspace(3) %gep1, align 8
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store i32 %val1, ptr addrspace(3) %out, align 8
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%gep2 = getelementptr i32, ptr addrspace(3) %out, i32 1
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store i32 %val2, ptr addrspace(3) %gep2, align 8
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ret void
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}
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; GCN-LABEL: {{^}}ds8align16:
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; GCN: ds_read_b128
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; GCN: ds_write_b128
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define amdgpu_kernel void @ds8align16(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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%val1 = load i64, ptr addrspace(3) %in, align 16
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%gep1 = getelementptr i64, ptr addrspace(3) %in, i64 1
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%val2 = load i64, ptr addrspace(3) %gep1, align 16
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store i64 %val1, ptr addrspace(3) %out, align 16
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%gep2 = getelementptr i64, ptr addrspace(3) %out, i64 1
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store i64 %val2, ptr addrspace(3) %gep2, align 16
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ret void
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}
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