derek.holloway
7502bf64a4
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38 lines
1.4 KiB
LLVM
38 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=-vsx| FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @copy_to_conceal(ptr %inp) #0 {
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; CHECK-LABEL: copy_to_conceal:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi 4, 1, -16
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; CHECK-NEXT: vxor 2, 2, 2
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; CHECK-NEXT: stvx 2, 0, 4
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; CHECK-NEXT: ld 4, -8(1)
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; CHECK-NEXT: std 4, 8(3)
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; CHECK-NEXT: ld 4, -16(1)
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; CHECK-NEXT: std 4, 0(3)
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; CHECK-NEXT: blr
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;
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; CHECK-VSX-LABEL: copy_to_conceal:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: xxlxor 0, 0, 0
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; CHECK-VSX-NEXT: stxvw4x 0, 0, 3
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; CHECK-VSX-NEXT: blr
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entry:
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store <8 x i16> zeroinitializer, ptr %inp, align 2
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br label %if.end210
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if.end210: ; preds = %entry
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ret void
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; This will generate two align-1 i64 stores. Make sure that they are
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; indexed stores and not in r+i form (which require the offset to be
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; a multiple of 4).
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" }
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