derek.holloway
7502bf64a4
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95 lines
2.9 KiB
LLVM
95 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
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@v256i64 = common dso_local local_unnamed_addr global <256 x i64> zeroinitializer, align 16
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; Function Attrs: norecurse nounwind readonly
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define fastcc <256 x i64> @loadv256i64(ptr nocapture readonly) {
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; CHECK-LABEL: loadv256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = load <256 x i64>, ptr %0, align 16
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ret <256 x i64> %2
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}
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; Function Attrs: norecurse nounwind readonly
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define fastcc <256 x double> @loadv256f64(ptr nocapture readonly) {
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; CHECK-LABEL: loadv256f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = load <256 x double>, ptr %0, align 16
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ret <256 x double> %2
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}
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; Function Attrs: norecurse nounwind readonly
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define fastcc <256 x i32> @loadv256i32(ptr nocapture readonly) {
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; CHECK-LABEL: loadv256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vldl.zx %v0, 4, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = load <256 x i32>, ptr %0, align 16
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ret <256 x i32> %2
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}
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; Function Attrs: norecurse nounwind readonly
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define fastcc <256 x float> @loadv256f32(ptr nocapture readonly) {
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; CHECK-LABEL: loadv256f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vldu %v0, 4, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = load <256 x float>, ptr %0, align 16
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ret <256 x float> %2
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}
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; Function Attrs: norecurse nounwind readonly
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define fastcc <256 x i64> @loadv256i64stk() {
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; CHECK-LABEL: loadv256i64stk:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s11, -2048(, %s11)
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; CHECK-NEXT: brge.l.t %s11, %s8, .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: ld %s61, 24(, %s14)
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; CHECK-NEXT: or %s62, 0, %s0
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; CHECK-NEXT: lea %s63, 315
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; CHECK-NEXT: shm.l %s63, (%s61)
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; CHECK-NEXT: shm.l %s8, 8(%s61)
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; CHECK-NEXT: shm.l %s11, 16(%s61)
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; CHECK-NEXT: monc
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; CHECK-NEXT: or %s0, 0, %s62
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lea %s1, (, %s11)
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vld %v0, 8, %s1
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; CHECK-NEXT: lea %s11, 2048(, %s11)
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; CHECK-NEXT: b.l.t (, %s10)
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%addr = alloca <256 x i64>, align 16
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%1 = load <256 x i64>, ptr %addr, align 16
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ret <256 x i64> %1
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}
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; Function Attrs: norecurse nounwind readonly
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define fastcc <256 x i64> @loadv256i64com() {
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; CHECK-LABEL: loadv256i64com:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, v256i64@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s0, v256i64@hi(, %s0)
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%1 = load <256 x i64>, ptr @v256i64, align 16
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ret <256 x i64> %1
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}
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