derek.holloway
7502bf64a4
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72 lines
1.8 KiB
TableGen
72 lines
1.8 KiB
TableGen
// RUN: not llvm-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t
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// RUN: FileCheck %s < %t
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include "llvm/Target/Target.td"
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def X0 : Register<"x0"> { let Namespace = "MyTarget"; }
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def GPR64 : RegisterClass<"MyTarget", [i64], 64, (add X0)>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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let Size = 4;
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bits<32> Inst;
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bits<32> SoftFail;
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}
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// Assume there is a 2 bit encoding for the dst and src register.
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def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
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bits<2> dst;
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bits<2> src1;
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let Inst{31...4} = 0;
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let Inst{1...0} = dst;
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let Inst{3...2} = src1;
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}
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def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
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bits<2> dst;
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bits<2> src1;
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let Inst{31...4} = 0;
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let Inst{1...0} = dst;
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let Inst{3...2} = src1;
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}
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def C : I<(outs GPR64:$dst), (ins GPR64:$src1), []> {
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bits<2> dst;
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bits<2> src1;
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let Inst{31...4} = 1;
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let Inst{1...0} = dst;
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let Inst{3...2} = src1;
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}
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def D : I<(outs GPR64:$dst), (ins GPR64:$src1), []> {
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bits<2> dst;
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bits<2> src1;
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let Inst{31...4} = 1;
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let Inst{1...0} = dst;
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let Inst{3...2} = src1;
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}
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// CHECK: Decoding Conflict:
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// CHECK: ................................
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// CHECK: 0000000000000000000000000000....
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// CHECK: 0000000000000000000000000000____ A
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// CHECK: 0000000000000000000000000000____ B
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// CHECK: Decoding Conflict:
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// CHECK: ................................
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// CHECK: 0000000000000000000000000001....
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// CHECK: 0000000000000000000000000001____ C
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// CHECK: 0000000000000000000000000001____ D
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// CHECK: Decoding conflict encountered
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