derek.holloway
7502bf64a4
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32 lines
1.3 KiB
C
32 lines
1.3 KiB
C
// REQUIRES: arm-registered-target
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// RUN: %clang_cc1 -triple armv7 -target-feature +neon %s -emit-llvm -o /dev/null
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char bar();
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void t1(int x, char y) {
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__asm__ volatile("mcr p15, 0, %1, c9, c12, 5;"
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"mrc p15, 0, %0, c9, c13, 2;"
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: "=r" (x)
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: "r" (bar())); // no warning
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__asm__ volatile("foo %0, %1"
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: "+r" (x),
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"+r" (y)
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:);
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__asm__ volatile("ldrb %0, [%1]" : "=r" (y) : "r" (x)); // no warning
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}
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typedef __attribute__((neon_vector_type(2))) long long int64x2_t;
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typedef struct int64x2x4_t {
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int64x2_t val[4];
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} int64x2x4_t;
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int64x2x4_t t2(const long long a[]) {
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int64x2x4_t r;
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__asm__("vldm %[a], { %q[r0], %q[r1], %q[r2], %q[r3] }"
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: [r0] "=r"(r.val[0]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
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[r1] "=r"(r.val[1]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
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[r2] "=r"(r.val[2]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
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[r3] "=r"(r.val[3]) // expected-warning {{value size does not match register size specified by the constraint and modifier}}
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: [a] "r"(a));
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return r;
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}
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