derek.holloway
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89 lines
2.9 KiB
YAML
89 lines
2.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: ashr_shl_to_sext_inreg
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: ashr_shl_to_sext_inreg
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[TRUNC]], 8
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)
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; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%1:_(s32) = COPY $w0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_CONSTANT i16 8
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%3:_(s16) = G_SHL %0, %2(s16)
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%4:_(s16) = exact G_ASHR %3, %2(s16)
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%5:_(s32) = G_ANYEXT %4(s16)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: different_shift_amts
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: different_shift_amts
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 12
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s16) = exact G_ASHR [[SHL]], [[C1]](s16)
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
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; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%1:_(s32) = COPY $w0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_CONSTANT i16 12
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%4:_(s16) = G_CONSTANT i16 8
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%3:_(s16) = G_SHL %0, %2(s16)
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%5:_(s16) = exact G_ASHR %3, %4(s16)
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%6:_(s32) = G_ANYEXT %5(s16)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: ashr_shl_to_sext_inreg_vector
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$d0' }
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body: |
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bb.1:
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liveins: $d0
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; CHECK-LABEL: name: ashr_shl_to_sext_inreg_vector
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s16>) = G_SEXT_INREG [[COPY]], 8
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; CHECK-NEXT: $d0 = COPY [[SEXT_INREG]](<4 x s16>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:_(<4 x s16>) = COPY $d0
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%2:_(s16) = G_CONSTANT i16 8
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%1:_(<4 x s16>) = G_BUILD_VECTOR %2(s16), %2(s16), %2(s16), %2(s16)
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%3:_(<4 x s16>) = G_SHL %0, %1(<4 x s16>)
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%4:_(<4 x s16>) = exact G_ASHR %3, %1(<4 x s16>)
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$d0 = COPY %4(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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