derek.holloway
7502bf64a4
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60 lines
2.6 KiB
LLVM
60 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -o - < %s | FileCheck --check-prefixes=GCN,GFX90A %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -o - < %s | FileCheck --check-prefixes=GCN,GFX90A %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -early-live-intervals -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s
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; GCN-LABEL: {{^}}gws_init_odd_reg:
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; GFX908-DAG: ds_gws_init v1 gds
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; GFX90A-DAG: ds_gws_init v2 gds
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; GCN-DAG: ds_gws_init v0 gds
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define amdgpu_ps void @gws_init_odd_reg(<2 x i32> %arg) {
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%vgpr.0 = extractelement <2 x i32> %arg, i32 0
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%vgpr.1 = extractelement <2 x i32> %arg, i32 1
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call void @llvm.amdgcn.ds.gws.init(i32 %vgpr.0, i32 0)
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call void @llvm.amdgcn.ds.gws.init(i32 %vgpr.1, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}gws_sema_br_odd_reg:
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; GFX908-DAG: ds_gws_sema_br v1 gds
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; GFX90A-DAG: ds_gws_sema_br v2 gds
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; GCN-DAG: ds_gws_sema_br v0 gds
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define amdgpu_ps void @gws_sema_br_odd_reg(<2 x i32> %arg) {
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%vgpr.0 = extractelement <2 x i32> %arg, i32 0
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%vgpr.1 = extractelement <2 x i32> %arg, i32 1
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call void @llvm.amdgcn.ds.gws.sema.br(i32 %vgpr.0, i32 0)
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call void @llvm.amdgcn.ds.gws.sema.br(i32 %vgpr.1, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}gws_barrier_odd_reg:
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; GFX908-DAG: ds_gws_barrier v1 gds
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; GFX90A-DAG: ds_gws_barrier v2 gds
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; GCN-DAG: ds_gws_barrier v0 gds
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define amdgpu_ps void @gws_barrier_odd_reg(<2 x i32> %arg) {
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%vgpr.0 = extractelement <2 x i32> %arg, i32 0
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%vgpr.1 = extractelement <2 x i32> %arg, i32 1
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call void @llvm.amdgcn.ds.gws.barrier(i32 %vgpr.0, i32 0)
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call void @llvm.amdgcn.ds.gws.barrier(i32 %vgpr.1, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}gws_init_odd_agpr:
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; GFX908-COUNT-2: ds_gws_init v{{[0-9]+}} gds
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; GFX90A-COUNT-2: ds_gws_init {{[va][0-9]?[02468]}} gds
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define amdgpu_ps void @gws_init_odd_agpr(<4 x i32> %arg) {
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bb:
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%mai = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 2, <4 x i32> %arg, i32 0, i32 0, i32 0)
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%agpr.0 = extractelement <4 x i32> %mai, i32 0
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%agpr.1 = extractelement <4 x i32> %mai, i32 1
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call void @llvm.amdgcn.ds.gws.init(i32 %agpr.0, i32 0)
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call void @llvm.amdgcn.ds.gws.init(i32 %agpr.1, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.ds.gws.init(i32, i32)
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declare void @llvm.amdgcn.ds.gws.sema.br(i32, i32)
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declare void @llvm.amdgcn.ds.gws.barrier(i32, i32)
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declare <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32, i32, <4 x i32>, i32, i32, i32)
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